From 1dbcfb228beadb4a243486506f3fe09b33b96f7d Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Mon, 2 Nov 2015 13:40:56 -0500 Subject: [PATCH 01/20] ARM: dts: NSP: Add PCI support Add PCI support to the Northstar Plus SoC. This uses the existing pcie-iproc driver. So, all that is needed is device tree entries in the DTS. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 74 +++++++++++++++++++++++++++++++- arch/arm/boot/dts/bcm958625k.dts | 12 ++++++ 2 files changed, 85 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 58aca277e4a7..85fb1c8a2421 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -96,7 +96,7 @@ periph_clk: periph_clk { axi { compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x00001000>; + ranges = <0x00000000 0x18000000 0x00015000>; #address-cells = <1>; #size-cells = <1>; @@ -115,5 +115,77 @@ uart1: serial@18000400 { clock-frequency = <62499840>; status = "disabled"; }; + + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x12000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; + + status = "disabled"; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x13000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; + + status = "disabled"; + }; + + pcie2: pcie@18014000 { + compatible = "brcm,iproc-pcie"; + reg = <0x14000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>; + + linux,pci-domain = <2>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 16303dbd35df..48592687cfeb 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -55,3 +55,15 @@ &uart0 { &uart1 { status = "okay"; }; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; From 41254754aa03ed8c223094799f1d3779c442aae4 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Mon, 2 Nov 2015 13:40:57 -0500 Subject: [PATCH 02/20] ARM: dts: NSP: Add NAND Support to DT Add NAND support to the device tree for the Broadcom Northstar Plus SoC. Since no driver changes are needed to enable this hardware, only the device tree changes are required to make this functional. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 16 +++++++++++++- arch/arm/boot/dts/bcm958625k.dts | 38 ++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 85fb1c8a2421..62bc86fca958 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -96,7 +96,7 @@ periph_clk: periph_clk { axi { compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x00015000>; + ranges = <0x00000000 0x18000000 0x0011ba08>; #address-cells = <1>; #size-cells = <1>; @@ -187,5 +187,19 @@ pcie2: pcie@18014000 { status = "disabled"; }; + + nand: nand@18026000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x026000 0x600>, + <0x11b408 0x600>, + <0x026f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; }; }; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 48592687cfeb..b966955260fa 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -67,3 +67,41 @@ &pcie1 { &pcie2 { status = "okay"; }; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@1 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@2 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@3 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; From 1a9d53cabaf4d3c57a65e7808a64eb7937abba11 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Mon, 2 Nov 2015 13:40:58 -0500 Subject: [PATCH 03/20] ARM: dts: NSP: Add TWD Support to DT Add support for the ARM TWD Timer and Watchdog to the Northstar Plus device tree. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 62bc86fca958..4bcdd28fd2ac 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -80,6 +80,22 @@ timer@19020200 { interrupts = ; clocks = <&periph_clk>; }; + + twd-timer@19020600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x0600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + twd-watchdog@19020620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x0620 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; }; clocks { From 445c0f29c1d0b771afc3b888bf375d73bb661e73 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Mon, 2 Nov 2015 13:34:52 -0500 Subject: [PATCH 04/20] dt-bindings: Add new SoCs to bcm4708 DT bindings Add the 4708, 4709, and 53012 SoCs to the the documentation for the Broadcom Northstar device tree bindings. Signed-off-by: Jon Mason Acked-by: Hauke Mehrtens Acked-by: Scott Branden Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt index 6b0f49f6f499..8608a776caa7 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt @@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties: Required root node property: +bcm4708 compatible = "brcm,bcm4708"; + +bcm4709 +compatible = "brcm,bcm4709"; + +bcm53012 +compatible = "brcm,bcm53012"; From ccf0b5e37115f8675455632f583d06ea94f43539 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Mon, 2 Nov 2015 13:34:53 -0500 Subject: [PATCH 05/20] ARM: dts: bcm5301x: Add BCM SVK DT files Add device tree files for Broadcom Northstar based SVKs. Since the bcm5301x.dtsi already exists, all that is necessary is the dts files to enable the UARTs. With these files, the SVKs are able to boot to shell. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 5 ++- arch/arm/boot/dts/bcm94708.dts | 56 ++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm94709.dts | 56 ++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm953012k.dts | 63 ++++++++++++++++++++++++++++++++ 4 files changed, 179 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/bcm94708.dts create mode 100644 arch/arm/boot/dts/bcm94709.dts create mode 100644 arch/arm/boot/dts/bcm953012k.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 30bbc3746130..eab8a7fb0341 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -75,7 +75,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4709-asus-rt-ac87u.dtb \ bcm4709-buffalo-wxr-1900dhp.dtb \ bcm4709-netgear-r7000.dtb \ - bcm4709-netgear-r8000.dtb + bcm4709-netgear-r8000.dtb \ + bcm94708.dtb \ + bcm94709.dtb \ + bcm953012k.dtb dtb-$(CONFIG_ARCH_BCM_63XX) += \ bcm963138dvt.dtb dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts new file mode 100644 index 000000000000..251a486f2da6 --- /dev/null +++ b/arch/arm/boot/dts/bcm94708.dts @@ -0,0 +1,56 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + model = "NorthStar SVK (BCM94708)"; + compatible = "brcm,bcm94708", "brcm,bcm4708"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts new file mode 100644 index 000000000000..b16cac92904f --- /dev/null +++ b/arch/arm/boot/dts/bcm94709.dts @@ -0,0 +1,56 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + model = "NorthStar SVK (BCM94709)"; + compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts new file mode 100644 index 000000000000..05a985a20378 --- /dev/null +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -0,0 +1,63 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + model = "NorthStar SVK (BCM953012K)"; + compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x00000000 0x10000000>; + }; +}; + +&uart0 { + clock-frequency = <62499840>; + status = "okay"; +}; + +&uart1 { + clock-frequency = <62499840>; + status = "okay"; +}; From 3890ab2bfb4579303cafb27225eb74ca568bd363 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Mon, 19 Oct 2015 11:13:10 +0530 Subject: [PATCH 06/20] dts: pinctrl: Add GPIO to Pinctrl pin mapping in DT ASIU gpio controller's pins are muxed with pin-cntroller. Add this mapping through property "gpio-ranges". Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Reviewed-by: Linus Walleij Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 53 +++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 2778533502d9..c9f1ac455e9a 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -248,10 +248,59 @@ gpio_asiu: gpio@180a5000 { #gpio-cells = <2>; gpio-controller; - pinmux = <&pinctrl>; - interrupt-controller; interrupts = ; + gpio-ranges = <&pinctrl 0 42 1>, + <&pinctrl 1 44 3>, + <&pinctrl 4 48 1>, + <&pinctrl 5 50 3>, + <&pinctrl 8 126 1>, + <&pinctrl 9 155 1>, + <&pinctrl 10 152 1>, + <&pinctrl 11 154 1>, + <&pinctrl 12 153 1>, + <&pinctrl 13 127 3>, + <&pinctrl 16 140 1>, + <&pinctrl 17 145 7>, + <&pinctrl 24 130 10>, + <&pinctrl 34 141 4>, + <&pinctrl 38 54 1>, + <&pinctrl 39 56 3>, + <&pinctrl 42 60 3>, + <&pinctrl 45 64 3>, + <&pinctrl 48 68 2>, + <&pinctrl 50 84 6>, + <&pinctrl 56 94 6>, + <&pinctrl 62 72 1>, + <&pinctrl 63 70 1>, + <&pinctrl 64 80 1>, + <&pinctrl 65 74 3>, + <&pinctrl 68 78 1>, + <&pinctrl 69 82 1>, + <&pinctrl 70 156 17>, + <&pinctrl 87 104 12>, + <&pinctrl 99 102 2>, + <&pinctrl 101 90 4>, + <&pinctrl 105 116 6>, + <&pinctrl 111 100 2>, + <&pinctrl 113 122 4>, + <&pinctrl 123 11 1>, + <&pinctrl 124 38 4>, + <&pinctrl 128 43 1>, + <&pinctrl 129 47 1>, + <&pinctrl 130 49 1>, + <&pinctrl 131 53 1>, + <&pinctrl 132 55 1>, + <&pinctrl 133 59 1>, + <&pinctrl 134 63 1>, + <&pinctrl 135 67 1>, + <&pinctrl 136 71 1>, + <&pinctrl 137 73 1>, + <&pinctrl 138 77 1>, + <&pinctrl 139 79 1>, + <&pinctrl 140 81 1>, + <&pinctrl 141 83 1>, + <&pinctrl 142 10 1>; }; touchscreen: tsc@180a6000 { From 7ba8cd8bf53adbc4ebdf1e684bf900f11327fcb8 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Tue, 17 Nov 2015 14:55:26 -0500 Subject: [PATCH 07/20] ARM: dts: NSP: Device Tree clean-ups Minor changes to the Broadcom Northstar Plus device tree to make it more organized and clean. Firstly, move the GIC and L2 cache entries to be sequential with respect to the memory addresses. Secondly, modify the address portion of the entry names to reflect the difference from the range modification. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 66 +++++++++++++++++----------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 4bcdd28fd2ac..7335a7478e3e 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -58,14 +58,30 @@ cpu@0 { }; }; - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x2000 0x1000>; - cache-unified; - cache-level = <2>; + timer@0200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x0200 0x100>; + interrupts = ; + clocks = <&periph_clk>; }; - gic: interrupt-controller@19021000 { + twd-timer@0600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x0600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + twd-watchdog@0620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x0620 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@1000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; @@ -74,27 +90,11 @@ gic: interrupt-controller@19021000 { <0x0100 0x100>; }; - timer@19020200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x0200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-timer@19020600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x0600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-watchdog@19020620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x0620 0x20>; - interrupts = ; - clocks = <&periph_clk>; + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x2000 0x1000>; + cache-unified; + cache-level = <2>; }; }; @@ -116,7 +116,7 @@ axi { #address-cells = <1>; #size-cells = <1>; - uart0: serial@18000300 { + uart0: serial@0300 { compatible = "ns16550a"; reg = <0x0300 0x100>; interrupts = ; @@ -124,7 +124,7 @@ uart0: serial@18000300 { status = "disabled"; }; - uart1: serial@18000400 { + uart1: serial@0400 { compatible = "ns16550a"; reg = <0x0400 0x100>; interrupts = ; @@ -132,7 +132,7 @@ uart1: serial@18000400 { status = "disabled"; }; - pcie0: pcie@18012000 { + pcie0: pcie@12000 { compatible = "brcm,iproc-pcie"; reg = <0x12000 0x1000>; @@ -156,7 +156,7 @@ pcie0: pcie@18012000 { status = "disabled"; }; - pcie1: pcie@18013000 { + pcie1: pcie@13000 { compatible = "brcm,iproc-pcie"; reg = <0x13000 0x1000>; @@ -180,7 +180,7 @@ pcie1: pcie@18013000 { status = "disabled"; }; - pcie2: pcie@18014000 { + pcie2: pcie@14000 { compatible = "brcm,iproc-pcie"; reg = <0x14000 0x1000>; @@ -204,7 +204,7 @@ pcie2: pcie@18014000 { status = "disabled"; }; - nand: nand@18026000 { + nand: nand@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x026000 0x600>, <0x11b408 0x600>, From 0f9f27a36d09580e1fd51e091dc99b15a895aa83 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Tue, 17 Nov 2015 14:55:27 -0500 Subject: [PATCH 08/20] ARM: dts: NSP: Add I2C support to the DT Add I2C support to the Broadcom Northstar Plus Device Tree. Since no driver changes are needed to enable this hardware, only the device tree changes are required to make this functional. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 7335a7478e3e..b74438c3d3ab 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -217,5 +217,14 @@ nand: nand@26000 { brcm,nand-has-wp; }; + + i2c0: i2c@38000 { + compatible = "brcm,iproc-i2c"; + reg = <0x38000 0x50>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + }; }; }; From cdc36b22f0e4b8badf3db14395f0aa44dcbce4b3 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 20 Nov 2015 10:17:18 -0500 Subject: [PATCH 09/20] ARM: dts: enable clock support for BCM5301X Replace current device tree dummy clocks with real clock support for Broadcom Northstar SoCs. Signed-off-by: Jon Mason Reviewed-by: Ray Jui Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 94 +++++++++++++++++++++++++-------- 1 file changed, 72 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 6f50f672efbd..65a1309bd6e2 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -8,6 +8,7 @@ * Licensed under the GNU/GPL. See COPYING for details. */ +#include #include #include #include @@ -27,7 +28,7 @@ uart0: serial@0300 { compatible = "ns16550"; reg = <0x0300 0x100>; interrupts = ; - clock-frequency = <100000000>; + clocks = <&iprocslow>; status = "disabled"; }; @@ -35,48 +36,55 @@ uart1: serial@0400 { compatible = "ns16550"; reg = <0x0400 0x100>; interrupts = ; - clock-frequency = <100000000>; + clocks = <&iprocslow>; status = "disabled"; }; }; mpcore { compatible = "simple-bus"; - ranges = <0x00000000 0x19020000 0x00003000>; + ranges = <0x00000000 0x19000000 0x00023000>; #address-cells = <1>; #size-cells = <1>; - scu@0000 { + a9pll: arm_clk@00000 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + scu@20000 { compatible = "arm,cortex-a9-scu"; - reg = <0x0000 0x100>; + reg = <0x20000 0x100>; }; - timer@0200 { + timer@20200 { compatible = "arm,cortex-a9-global-timer"; - reg = <0x0200 0x100>; + reg = <0x20200 0x100>; interrupts = ; - clocks = <&clk_periph>; + clocks = <&periph_clk>; }; - local-timer@0600 { + local-timer@20600 { compatible = "arm,cortex-a9-twd-timer"; - reg = <0x0600 0x100>; + reg = <0x20600 0x100>; interrupts = ; - clocks = <&clk_periph>; + clocks = <&periph_clk>; }; - gic: interrupt-controller@1000 { + gic: interrupt-controller@21000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x1000 0x1000>, - <0x0100 0x100>; + reg = <0x21000 0x1000>, + <0x20100 0x100>; }; - L2: cache-controller@2000 { + L2: cache-controller@22000 { compatible = "arm,pl310-cache"; - reg = <0x2000 0x1000>; + reg = <0x22000 0x1000>; cache-unified; arm,shared-override; prefetch-data = <1>; @@ -94,14 +102,37 @@ pmu { clocks { #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges; - /* As long as we do not have a real clock driver us this - * fixed clock */ - clk_periph: periph { - compatible = "fixed-clock"; + osc: oscillator { #clock-cells = <0>; - clock-frequency = <400000000>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; }; }; @@ -178,6 +209,25 @@ chipcommon: chipcommon@0 { }; }; + lcpll0: lcpll0@1800c100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x1800c100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", "sdio", + "ddr_phy"; + }; + + genpll: genpll@1800c140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x1800c140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", "ethernetclk", + "usbclk", "iprocfast", "sata1", + "sata2"; + }; + nand: nand@18028000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; From da3f974263a81c03b699b9d6ef2684c259526fde Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 20 Nov 2015 10:17:19 -0500 Subject: [PATCH 10/20] ARM: dts: enable clock support for Broadcom NSP Replace current device tree dummy clocks with real clock support for Broadcom Northstar Plus SoC Signed-off-by: Jon Mason Reviewed-by: Ray Jui Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 83 +++++++++++++++++++++++++++------- 1 file changed, 67 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index b74438c3d3ab..d9bfc5618c25 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -32,6 +32,7 @@ #include #include +#include #include "skeleton.dtsi" @@ -42,7 +43,7 @@ / { mpcore { compatible = "simple-bus"; - ranges = <0x00000000 0x19020000 0x00003000>; + ranges = <0x00000000 0x19000000 0x00023000>; #address-cells = <1>; #size-cells = <1>; @@ -58,41 +59,48 @@ cpu@0 { }; }; - timer@0200 { + a9pll: arm_clk@00000 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + timer@20200 { compatible = "arm,cortex-a9-global-timer"; - reg = <0x0200 0x100>; + reg = <0x20200 0x100>; interrupts = ; clocks = <&periph_clk>; }; - twd-timer@0600 { + twd-timer@20600 { compatible = "arm,cortex-a9-twd-timer"; - reg = <0x0600 0x20>; + reg = <0x20600 0x20>; interrupts = ; clocks = <&periph_clk>; }; - twd-watchdog@0620 { + twd-watchdog@20620 { compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x0620 0x20>; + reg = <0x20620 0x20>; interrupts = ; clocks = <&periph_clk>; }; - gic: interrupt-controller@1000 { + gic: interrupt-controller@21000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x1000 0x1000>, - <0x0100 0x100>; + reg = <0x21000 0x1000>, + <0x20100 0x100>; }; L2: l2-cache { compatible = "arm,pl310-cache"; - reg = <0x2000 0x1000>; + reg = <0x22000 0x1000>; cache-unified; cache-level = <2>; }; @@ -103,10 +111,34 @@ clocks { #size-cells = <1>; ranges; - periph_clk: periph_clk { - compatible = "fixed-clock"; + osc: oscillator { #clock-cells = <0>; - clock-frequency = <500000000>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; }; }; @@ -120,7 +152,7 @@ uart0: serial@0300 { compatible = "ns16550a"; reg = <0x0300 0x100>; interrupts = ; - clock-frequency = <62499840>; + clocks = <&osc>; status = "disabled"; }; @@ -128,7 +160,7 @@ uart1: serial@0400 { compatible = "ns16550a"; reg = <0x0400 0x100>; interrupts = ; - clock-frequency = <62499840>; + clocks = <&osc>; status = "disabled"; }; @@ -226,5 +258,24 @@ i2c0: i2c@38000 { interrupts = ; clock-frequency = <100000>; }; + + lcpll0: lcpll0@3f100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x3f100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", "sdio", + "ddr_phy"; + }; + + genpll: genpll@3f140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x3f140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", "ethernetclk", + "usbclk", "iprocfast", "sata1", + "sata2"; + }; }; }; From 5d3dc3938ee4649cbc47d1fd6f5716e798782ea5 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 29 Oct 2015 18:23:17 -0700 Subject: [PATCH 11/20] clk: iproc: Extend binding to cover BCM63138 Broadcom BCM63138 DSL SoCs have the same ARMPLL clocking infrastructure as the Cygnus and iProc chips, add a dedicated compatible string and document that the ARMPLL node is a valid node for this chip. Acked-by: Rob Herring Signed-off-by: Florian Fainelli Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/brcm,iproc-clocks.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index ede65a55e21b..0b35e71b39e8 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -208,3 +208,8 @@ These clock IDs are defined in: ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED + +BCM63138 +-------- +PLL and leaf clock compatible strings for BCM63138 are: + "brcm,bcm63138-armpll" From 7160aa1e5cdfb3fb8c0b6addb40c5f0e60cb0de0 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 29 Oct 2015 18:23:18 -0700 Subject: [PATCH 12/20] clk: bcm: Add BCM63138 clock support BCM63138 has a simple clocking domain which is primarily the ARMPLL clocking complex, from which the ARM (CPU), APB and AXI clocks would be derived from. Since the ARMPLL controller is entirely compatible with the iProc ARM PLL, we just initialize it without additional parameters. Signed-off-by: Florian Fainelli Signed-off-by: Stephen Boyd --- drivers/clk/bcm/Kconfig | 10 ++++++++++ drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-bcm63xx.c | 22 ++++++++++++++++++++++ 3 files changed, 33 insertions(+) create mode 100644 drivers/clk/bcm/clk-bcm63xx.c diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig index 85260fb96b36..f2878459199a 100644 --- a/drivers/clk/bcm/Kconfig +++ b/drivers/clk/bcm/Kconfig @@ -1,3 +1,13 @@ +config CLK_BCM_63XX + bool "Broadcom BCM63xx clock support" + depends on ARCH_BCM_63XX || COMPILE_TEST + depends on COMMON_CLK + select COMMON_CLK_IPROC + default ARCH_BCM_63XX + help + Enable common clock framework support for Broadcom BCM63xx DSL SoCs + based on the ARM architecture + config CLK_BCM_KONA bool "Broadcom Kona CCU clock support" depends on ARCH_BCM_MOBILE || COMPILE_TEST diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile index 3fc95060d875..247c26750d8b 100644 --- a/drivers/clk/bcm/Makefile +++ b/drivers/clk/bcm/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o diff --git a/drivers/clk/bcm/clk-bcm63xx.c b/drivers/clk/bcm/clk-bcm63xx.c new file mode 100644 index 000000000000..fbc17ae5ff2b --- /dev/null +++ b/drivers/clk/bcm/clk-bcm63xx.c @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2015 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include "clk-iproc.h" + +static void __init bcm63138_armpll_init(struct device_node *node) +{ + iproc_armpll_setup(node); +} +CLK_OF_DECLARE(bcm63138_armpll, "brcm,bcm63138-armpll", bcm63138_armpll_init); From 511d30443a1c3e8a358c044b14587cbf3ed27a46 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 29 Oct 2015 18:23:19 -0700 Subject: [PATCH 13/20] ARM: dts: BCM63xx: Add ARMPLL device tree nodes Add the ARM PLL controller which comes standard with the Cortex-A9 found on the BCM63138 SoCs. This is the same controller as the one found in the Broadcom iProc architecture, however, we have a separate compatible string to indicate the integration difference, since the hardware is different. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm63138.dtsi | 36 +++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index 34cd64051250..d0560e8cd6de 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -43,18 +43,31 @@ clocks { #address-cells = <1>; #size-cells = <0>; - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <500000000>; - }; - + /* UBUS peripheral clock */ periph_clk: periph_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; clock-output-names = "periph"; }; + + /* peripheral clock for system timer */ + axi_clk: axi_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&armpll>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* APB bus clock */ + apb_clk: apb_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&armpll>; + clock-div = <4>; + clock-mult = <1>; + }; }; /* ARM bus */ @@ -93,14 +106,14 @@ global_timer: timer@1e200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x1e200 0x20>; interrupts = ; - clocks = <&arm_timer_clk>; + clocks = <&axi_clk>; }; local_timer: local-timer@1e600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1e600 0x20>; interrupts = ; - clocks = <&arm_timer_clk>; + clocks = <&axi_clk>; }; twd_watchdog: watchdog@1e620 { @@ -109,6 +122,13 @@ twd_watchdog: watchdog@1e620 { interrupts = ; }; + armpll: armpll { + #clock-cells = <0>; + compatible = "brcm,bcm63138-armpll"; + clocks = <&periph_clk>; + reg = <0x20000 0xf00>; + }; + pmb0: reset-controller@4800c0 { compatible = "brcm,bcm63138-pmb"; reg = <0x4800c0 0x10>; From da41efd6041c694d93febdabee94552a2140dfbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 30 Oct 2015 15:44:01 +0100 Subject: [PATCH 14/20] ARM: BCM5301X: Add missing Netgear R8000 LEDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a bunch of LEDs missing for the Netgear R8000: wireless, wps, 5Ghz radio and USB LEDs. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 30 +++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index 446c586cd473..b52927c94e35 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -50,6 +50,36 @@ power1 { gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-off"; }; + + wireless { + label = "bcm53xx:white:wireless"; + gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + 5ghz-2 { + label = "bcm53xx:white:5ghz-2"; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + usb3 { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; }; gpio-keys { From 3ad8ff0e4ab3f908f93bd76afdad815060bb32db Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:14 +0530 Subject: [PATCH 15/20] ARM: dts: Cygnus: define ngpios property in gpio controller's node Add ngpios property in cygnus ASIU, CCM and CRMU gpio controller's node Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index c9f1ac455e9a..f8b75a53181b 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -101,6 +101,7 @@ gpio_crmu: gpio@03024800 { compatible = "brcm,cygnus-crmu-gpio"; reg = <0x03024800 0x50>, <0x03024008 0x18>; + ngpios = <6>; #gpio-cells = <2>; gpio-controller; }; @@ -127,6 +128,7 @@ gpio_ccm: gpio@1800a000 { compatible = "brcm,cygnus-ccm-gpio"; reg = <0x1800a000 0x50>, <0x0301d164 0x20>; + ngpios = <24>; #gpio-cells = <2>; gpio-controller; interrupts = ; @@ -245,6 +247,7 @@ nand: nand@18046000 { gpio_asiu: gpio@180a5000 { compatible = "brcm,cygnus-asiu-gpio"; reg = <0x180a5000 0x668>; + ngpios = <146>; #gpio-cells = <2>; gpio-controller; From 44a06fa4654d07a5ed63e1e0d67cdee1e20818e7 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Wed, 18 Nov 2015 10:16:59 -0800 Subject: [PATCH 16/20] ARM: dts: enable PCIe PHY support for Cygnus Enable PCIe PHY for both PCIe root complexes on Cygnus Signed-off-by: Ray Jui Acked-by: Scott Branden [florian: Fix missing #address-cells and #size-cells properties] Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index f8b75a53181b..815db5dd2f40 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -91,6 +91,23 @@ axi { #address-cells = <1>; #size-cells = <1>; + pcie_phy: phy@0301d0a0 { + compatible = "brcm,cygnus-pcie-phy"; + reg = <0x0301d0a0 0x14>; + #address-cells = <1>; + #size-cells = <0>; + + pcie0_phy: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + pcie1_phy: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + pinctrl: pinctrl@0x0301d0c8 { compatible = "brcm,cygnus-pinmux"; reg = <0x0301d0c8 0x30>, @@ -163,6 +180,9 @@ pcie0: pcie@18012000 { ranges = <0x81000000 0 0 0x28000000 0 0x00010000 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + phys = <&pcie0_phy>; + phy-names = "pcie-phy"; + status = "disabled"; }; @@ -184,6 +204,9 @@ pcie1: pcie@18013000 { ranges = <0x81000000 0 0 0x48000000 0 0x00010000 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + phys = <&pcie1_phy>; + phy-names = "pcie-phy"; + status = "disabled"; }; From ea2d8975e3f6600868a5ffe5d1089139c44abcf4 Mon Sep 17 00:00:00 2001 From: Yendapally Reddy Dhananjaya Reddy Date: Fri, 20 Nov 2015 12:58:29 -0500 Subject: [PATCH 17/20] ARM: dts: enable pinctrl for Broadcom NSP This enables the pinctrl support for Broadcom NSP SoC Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 7 +++++++ arch/arm/boot/dts/bcm958625k.dts | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index d9bfc5618c25..4214818df3a0 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -277,5 +277,12 @@ genpll: genpll@3f140 { "usbclk", "iprocfast", "sata1", "sata2"; }; + + pinctrl: pinctrl@3f1c0 { + compatible = "brcm,nsp-pinmux"; + reg = <0x3f1c0 0x04>, + <0x30028 0x04>, + <0x3f408 0x04>; + }; }; }; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index b966955260fa..e298450b49b2 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -105,3 +105,12 @@ partition@4 { }; }; }; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; From 7418111f88dfb92b33d9f765acba5fb45aefabeb Mon Sep 17 00:00:00 2001 From: Kapil Hali Date: Sat, 5 Dec 2015 06:53:40 -0500 Subject: [PATCH 18/20] dt-bindings: add SMP enable-method for Broadcom NSP Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's Northstar Plus CPU to the 32-bit ARM CPU device tree binding documentation file and create a new binding documentation for Northstar Plus CPU. Signed-off-by: Kapil Hali Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 +++++++++++++++++++ .../devicetree/bindings/arm/cpus.txt | 1 + 2 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file mode 100644 index 000000000000..677ef9d9f445 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt @@ -0,0 +1,39 @@ +Broadcom Northstar Plus SoC CPU Enable Method +--------------------------------------------- +This binding defines the enable method used for starting secondary +CPU in the following Broadcom SoCs: + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 + +The enable method is specified by defining the following required +properties in the corresponding secondary "cpu" device tree node: + - enable-method = "brcm,bcm-nsp-smp"; + - secondary-boot-reg = <...>; + +The secondary-boot-reg property is a u32 value that specifies the +physical address of the register which should hold the common +entry point for a secondary CPU. This entry is cpu node specific +and should be added per cpu. E.g., in case of NSP (BCM58625) which +is a dual core CPU SoC, this entry should be added to cpu1 node. + + +Example: + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + enable-method = "brcm,bcm-nsp-smp"; + secondary-boot-reg = <0xffff042c>; + reg = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3a07a87fef20..d1915549e009 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -190,6 +190,7 @@ nodes to be present and contain the properties described below. "allwinner,sun6i-a31" "allwinner,sun8i-a23" "arm,psci" + "brcm,bcm-nsp-smp" "brcm,brahma-b15" "marvell,armada-375-smp" "marvell,armada-380-smp" From 944725fcfff19d76205ac04d28e6e550ac2b3053 Mon Sep 17 00:00:00 2001 From: Kapil Hali Date: Sat, 5 Dec 2015 06:53:42 -0500 Subject: [PATCH 19/20] ARM: dts: Add SMP support for Broadcom NSP Add device tree changes required for providing SMP support for Broadcom Northstar Plus SoC. Signed-off-by: Kapil Hali Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 4214818df3a0..10bdef557ba0 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -41,6 +41,27 @@ / { model = "Broadcom Northstar Plus SoC"; interrupt-parent = <&gic>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + enable-method = "brcm,bcm-nsp-smp"; + secondary-boot-reg = <0xffff042c>; + reg = <0x1>; + }; + }; + mpcore { compatible = "simple-bus"; ranges = <0x00000000 0x19000000 0x00023000>; From f6b889358a82c1f1a34bfcecfe8ebf709deb28ec Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Fri, 4 Dec 2015 09:35:02 -0800 Subject: [PATCH 20/20] ARM: dts: Enable MSI support for Broadcom Cygnus Enable MSI support for Broadcom Cygnus platforms Signed-off-by: Ray Jui Reviewed-by: Anup Patel Reviewed-by: Pramod KUMAR Reviewed-by: Vikram Prakash Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 815db5dd2f40..3878793364f0 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -184,6 +184,17 @@ pcie0: pcie@18012000 { phy-names = "pcie-phy"; status = "disabled"; + + msi-parent = <&msi0>; + msi0: msi@18012000 { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; }; pcie1: pcie@18013000 { @@ -208,6 +219,17 @@ pcie1: pcie@18013000 { phy-names = "pcie-phy"; status = "disabled"; + + msi-parent = <&msi1>; + msi1: msi@18013000 { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; }; uart0: serial@18020000 {