mirror of
https://github.com/torvalds/linux.git
synced 2026-05-23 14:42:08 +02:00
Renesas ARM DT updates for v5.17
- Serial, SPI, timer, watchdog, operating points, and QSPI FLASH
support for the RZ/G2L SoC and the RZ/G2L SMARC EVK development
board,
- SDHI SDnH clocks for the R-Car Gen3 and RZ/G2 SoCs,
- Display Unit support for the R-Car V3U SoC,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.17
- Serial, SPI, timer, watchdog, operating points, and QSPI FLASH
support for the RZ/G2L SoC and the RZ/G2L SMARC EVK development
board,
- SDHI SDnH clocks for the R-Car Gen3 and RZ/G2 SoCs,
- Display Unit support for the R-Car V3U SoC,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits)
arm64: dts: renesas: r8a779a0: Add DU support
arm64: dts: renesas: salvator-common: Merge hdmi0_con
arm64: dts: renesas: ulcb: Merge hdmi0_con
arm64: dts: renesas: r9a07g044: Add OPP table
arm64: dts: renesas: Fix operating point table node names
arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog
arm64: dts: renesas: r9a07g044: Add WDT nodes
arm64: dts: renesas: r9a07g044: Rename SDHI clocks
arm64: dts: renesas: rzg2l-smarc-som: Enable serial NOR flash
arm64: dts: renesas: rzg2l-smarc-som: Enable OSTM
arm64: dts: renesas: r9a07g044: Add OSTM nodes
arm64: dts: renesas: r9a07g044: Sort psci node
arm64: dts: renesas: rzg2l-smarc: Enable RSPI1 on carrier board
arm64: dts: renesas: r9a07g044: Add RSPI{0,1,2} nodes
arm64: dts: renesas: cat875: Add rx/tx delays
arm64: dts: reneas: rcar-gen3: Add SDnH clocks
arm64: dts: reneas: rzg2: Add SDnH clocks
arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes
arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board
arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes
...
Link: https://lore.kernel.org/r/cover.1638530606.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
ee58c0a4d7
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|
@ -44,6 +44,22 @@ mclk_cam4: mclk-cam4 {
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|||
#clock-cells = <0>;
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||||
clock-frequency = <26000000>;
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||||
};
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||||
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reg_1p8v: 1p8v {
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compatible = "regulator-fixed";
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regulator-name = "1P8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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reg_2p8v: 2p8v {
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compatible = "regulator-fixed";
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regulator-name = "2P8V";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-always-on;
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};
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};
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&avb {
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@ -17,6 +17,9 @@ ov5640@3c {
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reg = <0x3c>;
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clocks = <&MCLK_CAM>;
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clock-names = "xclk";
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AVDD-supply = <®_2p8v>;
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DOVDD-supply = <®_2p8v>;
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DVDD-supply = <®_1p8v>;
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status = "okay";
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port {
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@ -18,6 +18,7 @@ &avb {
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pinctrl-names = "default";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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phy0: ethernet-phy@0 {
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@ -58,7 +58,7 @@ can_clk: can {
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clock-frequency = <0>;
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};
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cluster0_opp: opp_table0 {
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cluster0_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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@ -80,7 +80,7 @@ opp-1500000000 {
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};
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};
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cluster1_opp: opp_table1 {
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cluster1_opp: opp-table-1 {
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compatible = "operating-points-v2";
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opp-shared;
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@ -2276,7 +2276,8 @@ sdhi0: mmc@ee100000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee100000 0 0x2000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 314>;
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clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
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resets = <&cpg 314>;
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@ -2288,7 +2289,8 @@ sdhi1: mmc@ee120000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee120000 0 0x2000>;
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interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 313>;
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clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
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resets = <&cpg 313>;
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@ -2300,7 +2302,8 @@ sdhi2: mmc@ee140000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee140000 0 0x2000>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 312>;
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clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
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resets = <&cpg 312>;
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@ -2312,7 +2315,8 @@ sdhi3: mmc@ee160000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee160000 0 0x2000>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 311>;
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clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
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resets = <&cpg 311>;
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@ -47,7 +47,7 @@ can_clk: can {
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clock-frequency = <0>;
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};
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cluster0_opp: opp_table0 {
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cluster0_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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@ -2133,7 +2133,8 @@ sdhi0: mmc@ee100000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee100000 0 0x2000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 314>;
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clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
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resets = <&cpg 314>;
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||||
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@ -2145,7 +2146,8 @@ sdhi1: mmc@ee120000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee120000 0 0x2000>;
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interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 313>;
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clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
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resets = <&cpg 313>;
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@ -2157,7 +2159,8 @@ sdhi2: mmc@ee140000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee140000 0 0x2000>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 312>;
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clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
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resets = <&cpg 312>;
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@ -2169,7 +2172,8 @@ sdhi3: mmc@ee160000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee160000 0 0x2000>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 311>;
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clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
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resets = <&cpg 311>;
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@ -44,7 +44,7 @@ can_clk: can {
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clock-frequency = <0>;
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};
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cluster1_opp: opp_table10 {
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cluster1_opp: opp-table-1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-800000000 {
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@ -1626,7 +1626,8 @@ sdhi0: mmc@ee100000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee100000 0 0x2000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 314>;
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clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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resets = <&cpg 314>;
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@ -1638,7 +1639,8 @@ sdhi1: mmc@ee120000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee120000 0 0x2000>;
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interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 313>;
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clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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resets = <&cpg 313>;
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@ -1650,7 +1652,8 @@ sdhi3: mmc@ee160000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee160000 0 0x2000>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 311>;
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clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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resets = <&cpg 311>;
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|
|
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|
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@ -47,7 +47,7 @@ can_clk: can {
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clock-frequency = <0>;
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||||
};
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cluster0_opp: opp_table0 {
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cluster0_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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@ -69,7 +69,7 @@ opp-1500000000 {
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};
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};
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cluster1_opp: opp_table1 {
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cluster1_opp: opp-table-1 {
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compatible = "operating-points-v2";
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opp-shared;
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@ -2362,7 +2362,8 @@ sdhi0: mmc@ee100000 {
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee100000 0 0x2000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&cpg CPG_MOD 314>;
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clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;
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clock-names = "core", "clkh";
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max-frequency = <200000000>;
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power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
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resets = <&cpg 314>;
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|
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@ -2375,7 +2376,8 @@ sdhi1: mmc@ee120000 {
|
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee120000 0 0x2000>;
|
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interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
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clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2388,7 +2390,8 @@ sdhi2: mmc@ee140000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2401,7 +2404,8 @@ sdhi3: mmc@ee160000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ can_clk: can {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -96,7 +96,7 @@ opp-1700000000 {
|
|||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -2668,7 +2668,8 @@ sdhi0: mmc@ee100000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -2681,7 +2682,8 @@ sdhi1: mmc@ee120000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2694,7 +2696,8 @@ sdhi2: mmc@ee140000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2707,7 +2710,8 @@ sdhi3: mmc@ee160000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ can_clk: can {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -97,7 +97,7 @@ opp-1800000000 {
|
|||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -2468,7 +2468,8 @@ sdhi0: mmc@ee100000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -2481,7 +2482,8 @@ sdhi1: mmc@ee120000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2494,7 +2496,8 @@ sdhi2: mmc@ee140000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2507,7 +2510,8 @@ sdhi3: mmc@ee160000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ can_clk: can {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -86,7 +86,7 @@ opp-1800000000 {
|
|||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -2312,7 +2312,8 @@ sdhi0: mmc@ee100000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77961_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -2325,7 +2326,8 @@ sdhi1: mmc@ee120000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77961_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2338,7 +2340,8 @@ sdhi2: mmc@ee140000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77961_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2351,7 +2354,8 @@ sdhi3: mmc@ee160000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77961_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ can_clk: can {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -2315,7 +2315,8 @@ sdhi0: mmc@ee100000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -2328,7 +2329,8 @@ sdhi1: mmc@ee120000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2341,7 +2343,8 @@ sdhi2: mmc@ee140000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2354,7 +2357,8 @@ sdhi3: mmc@ee160000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
|
|||
|
|
@ -1339,7 +1339,8 @@ mmc0: mmc@ee140000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
max-frequency = <200000000>;
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ can_clk: can {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table10 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp-800000000 {
|
||||
|
|
@ -1788,7 +1788,8 @@ sdhi0: mmc@ee100000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77990_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -1801,7 +1802,8 @@ sdhi1: mmc@ee120000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77990_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -1814,7 +1816,8 @@ sdhi3: mmc@ee160000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77990_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
|
|||
|
|
@ -1216,7 +1216,8 @@ sdhi2: mmc@ee140000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
|
|||
|
|
@ -1993,7 +1993,8 @@ mmc0: mmc@ee140000 {
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 706>;
|
||||
clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779A0_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 706>;
|
||||
max-frequency = <200000000>;
|
||||
|
|
@ -2268,6 +2269,38 @@ csi43isp3: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a779a0";
|
||||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 411>;
|
||||
clock-names = "du.0";
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 411>;
|
||||
reset-names = "du.0";
|
||||
renesas,vsps = <&vspd0 0>, <&vspd1 0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_dsi0: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_dsi1: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
isp0: isp@fed00000 {
|
||||
compatible = "renesas,r8a779a0-isp";
|
||||
reg = <0 0xfed00000 0 0x10000>;
|
||||
|
|
|
|||
|
|
@ -42,9 +42,31 @@ extal_clk: extal {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-150000000 {
|
||||
opp-hz = /bits/ 64 <150000000>;
|
||||
opp-microvolt = <1100000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <1100000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <1100000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <1100000>;
|
||||
clock-latency-ns = <300000>;
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -68,6 +90,8 @@ cpu0: cpu@0 {
|
|||
device_type = "cpu";
|
||||
next-level-cache = <&L3_CA55>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu1: cpu@100 {
|
||||
|
|
@ -76,6 +100,8 @@ cpu1: cpu@100 {
|
|||
device_type = "cpu";
|
||||
next-level-cache = <&L3_CA55>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
L3_CA55: cache-controller-0 {
|
||||
|
|
@ -85,6 +111,11 @@ L3_CA55: cache-controller-0 {
|
|||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -176,6 +207,54 @@ ssi3: ssi@1004a800 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@1004ac00 {
|
||||
compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
|
||||
reg = <0 0x1004ac00 0 0x400>;
|
||||
interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error", "rx", "tx";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
|
||||
resets = <&cpg R9A07G044_RSPI0_RST>;
|
||||
power-domains = <&cpg>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@1004b000 {
|
||||
compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
|
||||
reg = <0 0x1004b000 0 0x400>;
|
||||
interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error", "rx", "tx";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
|
||||
resets = <&cpg R9A07G044_RSPI1_RST>;
|
||||
power-domains = <&cpg>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@1004b400 {
|
||||
compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
|
||||
reg = <0 0x1004b400 0 0x400>;
|
||||
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error", "rx", "tx";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
|
||||
resets = <&cpg R9A07G044_RSPI2_RST>;
|
||||
power-domains = <&cpg>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif0: serial@1004b800 {
|
||||
compatible = "renesas,scif-r9a07g044";
|
||||
reg = <0 0x1004b800 0 0x400>;
|
||||
|
|
@ -194,6 +273,108 @@ scif0: serial@1004b800 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
scif1: serial@1004bc00 {
|
||||
compatible = "renesas,scif-r9a07g044";
|
||||
reg = <0 0x1004bc00 0 0x400>;
|
||||
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "eri", "rxi", "txi",
|
||||
"bri", "dri", "tei";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif2: serial@1004c000 {
|
||||
compatible = "renesas,scif-r9a07g044";
|
||||
reg = <0 0x1004c000 0 0x400>;
|
||||
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "eri", "rxi", "txi",
|
||||
"bri", "dri", "tei";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif3: serial@1004c400 {
|
||||
compatible = "renesas,scif-r9a07g044";
|
||||
reg = <0 0x1004c400 0 0x400>;
|
||||
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "eri", "rxi", "txi",
|
||||
"bri", "dri", "tei";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif4: serial@1004c800 {
|
||||
compatible = "renesas,scif-r9a07g044";
|
||||
reg = <0 0x1004c800 0 0x400>;
|
||||
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "eri", "rxi", "txi",
|
||||
"bri", "dri", "tei";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sci0: serial@1004d000 {
|
||||
compatible = "renesas,r9a07g044-sci", "renesas,sci";
|
||||
reg = <0 0x1004d000 0 0x400>;
|
||||
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "eri", "rxi", "txi", "tei";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G044_SCI0_RST>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sci1: serial@1004d400 {
|
||||
compatible = "renesas,r9a07g044-sci", "renesas,sci";
|
||||
reg = <0 0x1004d400 0 0x400>;
|
||||
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "eri", "rxi", "txi", "tei";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G044_SCI1_RST>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
canfd: can@10050000 {
|
||||
compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
|
||||
reg = <0 0x10050000 0 0x8000>;
|
||||
|
|
@ -463,10 +644,10 @@ sdhi0: mmc@11c00000 {
|
|||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
|
||||
<&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
|
||||
<&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
|
||||
<&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
|
||||
<&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
|
||||
clock-names = "imclk", "imclk2", "clk_hs", "aclk";
|
||||
clock-names = "core", "clkh", "cd", "aclk";
|
||||
resets = <&cpg R9A07G044_SDHI0_IXRST>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
|
|
@ -479,10 +660,10 @@ sdhi1: mmc@11c10000 {
|
|||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
|
||||
<&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
|
||||
<&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
|
||||
<&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
|
||||
<&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
|
||||
clock-names = "imclk", "imclk2", "clk_hs", "aclk";
|
||||
clock-names = "core", "clkh", "cd", "aclk";
|
||||
resets = <&cpg R9A07G044_SDHI1_IXRST>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
|
|
@ -641,6 +822,84 @@ hsusb: usb@11c60000 {
|
|||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt0: watchdog@12800800 {
|
||||
compatible = "renesas,r9a07g044-wdt",
|
||||
"renesas,rzg2l-wdt";
|
||||
reg = <0 0x12800800 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
|
||||
<&cpg CPG_MOD R9A07G044_WDT0_CLK>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "wdt", "perrout";
|
||||
resets = <&cpg R9A07G044_WDT0_PRESETN>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt1: watchdog@12800c00 {
|
||||
compatible = "renesas,r9a07g044-wdt",
|
||||
"renesas,rzg2l-wdt";
|
||||
reg = <0 0x12800C00 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
|
||||
<&cpg CPG_MOD R9A07G044_WDT1_CLK>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "wdt", "perrout";
|
||||
resets = <&cpg R9A07G044_WDT1_PRESETN>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt2: watchdog@12800400 {
|
||||
compatible = "renesas,r9a07g044-wdt",
|
||||
"renesas,rzg2l-wdt";
|
||||
reg = <0 0x12800400 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
|
||||
<&cpg CPG_MOD R9A07G044_WDT2_CLK>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "wdt", "perrout";
|
||||
resets = <&cpg R9A07G044_WDT2_PRESETN>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm0: timer@12801000 {
|
||||
compatible = "renesas,r9a07g044-ostm",
|
||||
"renesas,ostm";
|
||||
reg = <0x0 0x12801000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
|
||||
resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm1: timer@12801400 {
|
||||
compatible = "renesas,r9a07g044-ostm",
|
||||
"renesas,ostm";
|
||||
reg = <0x0 0x12801400 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
|
||||
resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm2: timer@12801800 {
|
||||
compatible = "renesas,r9a07g044-ostm",
|
||||
"renesas,ostm";
|
||||
reg = <0x0 0x12801800 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
|
||||
resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
|
|
@ -130,6 +130,14 @@ &extal_clk {
|
|||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&ostm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
adc_pins: adc {
|
||||
pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
|
||||
|
|
@ -178,6 +186,18 @@ gpio-sd0-pwr-en-hog {
|
|||
line-name = "gpio_sd0_pwr_en";
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
qspi0-data {
|
||||
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
qspi0-ctrl {
|
||||
pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
|
||||
power-source = <1800>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
|
||||
* The below switch logic can be used to select the device between
|
||||
|
|
@ -243,6 +263,34 @@ sd0_mux_uhs {
|
|||
};
|
||||
};
|
||||
|
||||
&sbc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "micron,mt25qu512a", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
m25p,fast-read;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
boot@0 {
|
||||
reg = <0x00000000 0x2000000>;
|
||||
read-only;
|
||||
};
|
||||
user@2000000 {
|
||||
reg = <0x2000000 0x2000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#if SDHI
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
|
|
@ -273,3 +321,18 @@ &sdhi0 {
|
|||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&wdt0 {
|
||||
status = "okay";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
||||
&wdt1 {
|
||||
status = "okay";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
||||
&wdt2 {
|
||||
status = "okay";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,9 +21,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
|
||||
#define PMOD1_SER0 1
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
serial1 = &scif2;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c3 = &i2c3;
|
||||
|
|
@ -208,6 +212,13 @@ scif0_pins: scif0 {
|
|||
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
|
||||
<RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
|
||||
<RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
|
||||
<RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
|
||||
};
|
||||
|
||||
sd1-pwr-en-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
|
||||
|
|
@ -252,6 +263,13 @@ sound_clk_pins: sound_clk {
|
|||
input-enable;
|
||||
};
|
||||
|
||||
spi1_pins: spi1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
|
||||
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
|
||||
<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
|
||||
<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
|
||||
};
|
||||
|
||||
ssi0_pins: ssi0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
|
||||
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
|
||||
|
|
@ -277,6 +295,23 @@ &scif0 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* To enable SCIF2 (SER0) on PMOD1 (CN7)
|
||||
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
|
||||
* SW2 should be at position 2->3 so that SER0_TX line is activated
|
||||
* SW3 should be at position 2->3 so that SER0_RX line is activated
|
||||
* SW4 should be at position 2->3 so that SER0_RTS# line is activated
|
||||
*/
|
||||
#if PMOD1_SER0
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
|
|
@ -290,6 +325,13 @@ &sdhi1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi0 {
|
||||
pinctrl-0 = <&ssi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -97,6 +97,7 @@ hdmi0-out {
|
|||
|
||||
port {
|
||||
hdmi0_con: endpoint {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -424,10 +425,6 @@ dw_hdmi0_snd_in: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
#ifdef SOC_HAS_HDMI1
|
||||
&hdmi1 {
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@ hdmi0-out {
|
|||
|
||||
port {
|
||||
hdmi0_con: endpoint {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -199,10 +200,6 @@ dw_hdmi0_snd_in: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user