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arm64: dts: mt8195: Add venc node
Add venc node for mt8195 SoC. Signed-off-by: Irui Wang <irui.wang@mediatek.com> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221103025656.8714-4-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -1962,6 +1962,30 @@ larb19: larb@1a010000 {
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power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
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};
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venc: video-codec@1a020000 {
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compatible = "mediatek,mt8195-vcodec-enc";
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reg = <0 0x1a020000 0 0x10000>;
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iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
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<&iommu_vdo M4U_PORT_L19_VENC_REC>,
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<&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
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<&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
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<&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
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<&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
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<&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
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<&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
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<&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
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interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
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mediatek,scp = <&scp>;
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clocks = <&vencsys CLK_VENC_VENC>;
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clock-names = "venc_sel";
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assigned-clocks = <&topckgen CLK_TOP_VENC>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
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};
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vencsys_core1: clock-controller@1b000000 {
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compatible = "mediatek,mt8195-vencsys_core1";
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reg = <0 0x1b000000 0 0x1000>;
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