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drm/msm/a8xx: Implement IFPC support for A840
Implement pwrup reglist support and add the necessary register configurations to enable IFPC support on A840 Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/714679/ Message-ID: <20260327-a8xx-gpu-batch2-v2-14-2b53c38d2101@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Akhil P Oommen
Rob Clark
parent
dd108bb9da
commit
ee37487ffe
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@ -1891,6 +1891,185 @@ static const struct adreno_reglist a840_gbif[] = {
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{ },
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};
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static const uint32_t a840_pwrup_reglist_regs[] = {
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REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP,
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REG_A7XX_SP_READ_SEL,
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REG_A6XX_UCHE_MODE_CNTL,
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REG_A8XX_UCHE_VARB_IDLE_TIMEOUT,
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REG_A8XX_UCHE_GBIF_GX_CONFIG,
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REG_A8XX_UCHE_CCHE_MODE_CNTL,
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REG_A8XX_UCHE_CCHE_CACHE_WAYS,
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REG_A8XX_UCHE_CACHE_WAYS,
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REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN,
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REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1,
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REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN,
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REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN + 1,
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REG_A8XX_UCHE_CCHE_TRAP_BASE,
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REG_A8XX_UCHE_CCHE_TRAP_BASE + 1,
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REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE,
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REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1,
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REG_A8XX_UCHE_HW_DBG_CNTL,
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REG_A8XX_UCHE_WRITE_THRU_BASE,
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REG_A8XX_UCHE_WRITE_THRU_BASE + 1,
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REG_A8XX_UCHE_TRAP_BASE,
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REG_A8XX_UCHE_TRAP_BASE + 1,
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REG_A8XX_UCHE_CLIENT_PF,
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REG_A8XX_RB_CMP_NC_MODE_CNTL,
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REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN,
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REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1,
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REG_A6XX_TPL1_NC_MODE_CNTL,
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REG_A6XX_TPL1_DBG_ECO_CNTL,
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REG_A6XX_TPL1_DBG_ECO_CNTL1,
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19),
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};
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DECLARE_ADRENO_REGLIST_LIST(a840_pwrup_reglist);
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static const u32 a840_ifpc_reglist_regs[] = {
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REG_A8XX_RBBM_NC_MODE_CNTL,
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REG_A8XX_RBBM_SLICE_NC_MODE_CNTL,
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REG_A6XX_SP_NC_MODE_CNTL,
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REG_A6XX_SP_CHICKEN_BITS,
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REG_A8XX_SP_SS_CHICKEN_BITS_0,
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REG_A7XX_SP_CHICKEN_BITS_1,
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REG_A7XX_SP_CHICKEN_BITS_2,
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REG_A7XX_SP_CHICKEN_BITS_3,
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REG_A8XX_SP_CHICKEN_BITS_4,
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REG_A6XX_SP_PERFCTR_SHADER_MASK,
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REG_A8XX_RBBM_SLICE_PERFCTR_CNTL,
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REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL,
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REG_A7XX_SP_HLSQ_DBG_ECO_CNTL,
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REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1,
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REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2,
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REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3,
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REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN,
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REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN + 1,
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REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL,
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REG_A8XX_RBBM_PERFCTR_CNTL,
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REG_A8XX_CP_PROTECT_GLOBAL(0),
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REG_A8XX_CP_PROTECT_GLOBAL(1),
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REG_A8XX_CP_PROTECT_GLOBAL(2),
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REG_A8XX_CP_PROTECT_GLOBAL(3),
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REG_A8XX_CP_PROTECT_GLOBAL(4),
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REG_A8XX_CP_PROTECT_GLOBAL(5),
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REG_A8XX_CP_PROTECT_GLOBAL(6),
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REG_A8XX_CP_PROTECT_GLOBAL(7),
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REG_A8XX_CP_PROTECT_GLOBAL(8),
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REG_A8XX_CP_PROTECT_GLOBAL(9),
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REG_A8XX_CP_PROTECT_GLOBAL(10),
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REG_A8XX_CP_PROTECT_GLOBAL(11),
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REG_A8XX_CP_PROTECT_GLOBAL(12),
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REG_A8XX_CP_PROTECT_GLOBAL(13),
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REG_A8XX_CP_PROTECT_GLOBAL(14),
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REG_A8XX_CP_PROTECT_GLOBAL(15),
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REG_A8XX_CP_PROTECT_GLOBAL(16),
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REG_A8XX_CP_PROTECT_GLOBAL(17),
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REG_A8XX_CP_PROTECT_GLOBAL(18),
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REG_A8XX_CP_PROTECT_GLOBAL(19),
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REG_A8XX_CP_PROTECT_GLOBAL(20),
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REG_A8XX_CP_PROTECT_GLOBAL(21),
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REG_A8XX_CP_PROTECT_GLOBAL(22),
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REG_A8XX_CP_PROTECT_GLOBAL(23),
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REG_A8XX_CP_PROTECT_GLOBAL(24),
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REG_A8XX_CP_PROTECT_GLOBAL(25),
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REG_A8XX_CP_PROTECT_GLOBAL(26),
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REG_A8XX_CP_PROTECT_GLOBAL(27),
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REG_A8XX_CP_PROTECT_GLOBAL(28),
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REG_A8XX_CP_PROTECT_GLOBAL(29),
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REG_A8XX_CP_PROTECT_GLOBAL(30),
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REG_A8XX_CP_PROTECT_GLOBAL(31),
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REG_A8XX_CP_PROTECT_GLOBAL(32),
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REG_A8XX_CP_PROTECT_GLOBAL(33),
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REG_A8XX_CP_PROTECT_GLOBAL(34),
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REG_A8XX_CP_PROTECT_GLOBAL(35),
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REG_A8XX_CP_PROTECT_GLOBAL(36),
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REG_A8XX_CP_PROTECT_GLOBAL(37),
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REG_A8XX_CP_PROTECT_GLOBAL(38),
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REG_A8XX_CP_PROTECT_GLOBAL(39),
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REG_A8XX_CP_PROTECT_GLOBAL(40),
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REG_A8XX_CP_PROTECT_GLOBAL(41),
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REG_A8XX_CP_PROTECT_GLOBAL(42),
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REG_A8XX_CP_PROTECT_GLOBAL(43),
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REG_A8XX_CP_PROTECT_GLOBAL(44),
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REG_A8XX_CP_PROTECT_GLOBAL(45),
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REG_A8XX_CP_PROTECT_GLOBAL(46),
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REG_A8XX_CP_PROTECT_GLOBAL(47),
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REG_A8XX_CP_PROTECT_GLOBAL(48),
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REG_A8XX_CP_PROTECT_GLOBAL(49),
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REG_A8XX_CP_PROTECT_GLOBAL(50),
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REG_A8XX_CP_PROTECT_GLOBAL(51),
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REG_A8XX_CP_PROTECT_GLOBAL(52),
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REG_A8XX_CP_PROTECT_GLOBAL(53),
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REG_A8XX_CP_PROTECT_GLOBAL(54),
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REG_A8XX_CP_PROTECT_GLOBAL(55),
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REG_A8XX_CP_PROTECT_GLOBAL(56),
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REG_A8XX_CP_PROTECT_GLOBAL(57),
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REG_A8XX_CP_PROTECT_GLOBAL(58),
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REG_A8XX_CP_PROTECT_GLOBAL(59),
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REG_A8XX_CP_PROTECT_GLOBAL(60),
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REG_A8XX_CP_PROTECT_GLOBAL(61),
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REG_A8XX_CP_PROTECT_GLOBAL(62),
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REG_A8XX_CP_PROTECT_GLOBAL(63),
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};
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DECLARE_ADRENO_REGLIST_LIST(a840_ifpc_reglist);
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static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = {
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{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)},
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{ REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A6XX_RB_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
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BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
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BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
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{ REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
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BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
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BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
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{ REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)},
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{ REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) },
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{ REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
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{ REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
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{ REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) },
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};
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DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist);
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static const struct adreno_info a8xx_gpus[] = {
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{
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.chip_ids = ADRENO_CHIP_IDS(0x44070001),
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@ -1940,11 +2119,15 @@ static const struct adreno_info a8xx_gpus[] = {
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.gmem = 18 * SZ_1M,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
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ADRENO_QUIRK_HAS_HW_APRIV,
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ADRENO_QUIRK_HAS_HW_APRIV |
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ADRENO_QUIRK_IFPC,
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.funcs = &a8xx_gpu_funcs,
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.a6xx = &(const struct a6xx_info) {
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.protect = &a840_protect,
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.nonctxt_reglist = a840_nonctxt_regs,
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.pwrup_reglist = &a840_pwrup_reglist,
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.dyn_pwrup_reglist = &a840_dyn_pwrup_reglist,
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.ifpc_reglist = &a840_ifpc_reglist,
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.gbif_cx = a840_gbif,
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.max_slices = 3,
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.gmu_chipid = 0x8020100,
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@ -183,7 +183,7 @@ void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
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/* Update HW if this is the current ring and we are not in preempt*/
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if (!a6xx_in_preempt(a6xx_gpu)) {
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if (a6xx_gpu->cur_ring == ring)
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gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
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a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false);
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else
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ring->restore_wptr = true;
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} else {
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@ -396,8 +396,87 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect)
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a8xx_aperture_clear(gpu);
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}
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static void a8xx_patch_pwrup_reglist(struct msm_gpu *gpu)
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{
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const struct adreno_reglist_pipe_list *dyn_pwrup_reglist;
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
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const struct adreno_reglist_list *reglist;
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void *ptr = a6xx_gpu->pwrup_reglist_ptr;
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struct cpu_gpu_lock *lock = ptr;
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u32 *dest = (u32 *)&lock->regs[0];
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u32 dyn_pwrup_reglist_count = 0;
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int i;
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lock->gpu_req = lock->cpu_req = lock->turn = 0;
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reglist = adreno_gpu->info->a6xx->ifpc_reglist;
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if (reglist) {
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lock->ifpc_list_len = reglist->count;
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/*
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* For each entry in each of the lists, write the offset and the current
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* register value into the GPU buffer
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*/
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for (i = 0; i < reglist->count; i++) {
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*dest++ = reglist->regs[i];
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*dest++ = gpu_read(gpu, reglist->regs[i]);
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}
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}
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reglist = adreno_gpu->info->a6xx->pwrup_reglist;
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if (reglist) {
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lock->preemption_list_len = reglist->count;
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for (i = 0; i < reglist->count; i++) {
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*dest++ = reglist->regs[i];
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*dest++ = gpu_read(gpu, reglist->regs[i]);
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}
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}
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/*
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* The overall register list is composed of
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* 1. Static IFPC-only registers
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* 2. Static IFPC + preemption registers
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* 3. Dynamic IFPC + preemption registers (ex: perfcounter selects)
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*
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* The first two lists are static. Size of these lists are stored as
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* number of pairs in ifpc_list_len and preemption_list_len
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* respectively. With concurrent binning, Some of the perfcounter
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* registers being virtualized, CP needs to know the pipe id to program
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* the aperture inorder to restore the same. Thus, third list is a
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* dynamic list with triplets as
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* (<aperture, shifted 12 bits> <address> <data>), and the length is
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* stored as number for triplets in dynamic_list_len.
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*/
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dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist;
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if (!dyn_pwrup_reglist)
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goto done;
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for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_DDE_BV; pipe_id++) {
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for (i = 0; i < dyn_pwrup_reglist->count; i++) {
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if (!(dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id)))
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continue;
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*dest++ = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe_id);
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*dest++ = dyn_pwrup_reglist->regs[i].offset;
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*dest++ = a8xx_read_pipe_slice(gpu,
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pipe_id,
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a8xx_get_first_slice(a6xx_gpu),
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dyn_pwrup_reglist->regs[i].offset);
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dyn_pwrup_reglist_count++;
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}
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}
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lock->dynamic_list_len = dyn_pwrup_reglist_count;
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done:
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a8xx_aperture_clear(gpu);
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}
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static int a8xx_cp_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
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struct msm_ringbuffer *ring = gpu->rb[0];
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u32 mask;
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@ -405,7 +484,7 @@ static int a8xx_cp_init(struct msm_gpu *gpu)
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OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
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OUT_RING(ring, BIT(27));
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OUT_PKT7(ring, CP_ME_INIT, 4);
|
||||
OUT_PKT7(ring, CP_ME_INIT, 7);
|
||||
|
||||
/* Use multiple HW contexts */
|
||||
mask = BIT(0);
|
||||
|
|
@ -419,6 +498,9 @@ static int a8xx_cp_init(struct msm_gpu *gpu)
|
|||
/* Disable save/restore of performance counters across preemption */
|
||||
mask |= BIT(6);
|
||||
|
||||
/* Enable the register init list with the spinlock */
|
||||
mask |= BIT(8);
|
||||
|
||||
OUT_RING(ring, mask);
|
||||
|
||||
/* Enable multiple hardware contexts */
|
||||
|
|
@ -430,6 +512,14 @@ static int a8xx_cp_init(struct msm_gpu *gpu)
|
|||
/* Operation mode mask */
|
||||
OUT_RING(ring, 0x00000002);
|
||||
|
||||
/* Lo address */
|
||||
OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova));
|
||||
/* Hi address */
|
||||
OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova));
|
||||
|
||||
/* Enable dyn pwrup list with triplets (offset, value, pipe) */
|
||||
OUT_RING(ring, BIT(31));
|
||||
|
||||
a6xx_flush(gpu, ring);
|
||||
return a8xx_idle(gpu, ring) ? 0 : -EINVAL;
|
||||
}
|
||||
|
|
@ -712,6 +802,11 @@ static int hw_init(struct msm_gpu *gpu)
|
|||
WARN_ON(!gmem_protect);
|
||||
a8xx_aperture_clear(gpu);
|
||||
|
||||
if (!a6xx_gpu->pwrup_reglist_emitted) {
|
||||
a8xx_patch_pwrup_reglist(gpu);
|
||||
a6xx_gpu->pwrup_reglist_emitted = true;
|
||||
}
|
||||
|
||||
/* Enable hardware clockgating */
|
||||
a8xx_set_hwcg(gpu, true);
|
||||
out:
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user