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ASoC: Intel: cht_bsw_rt5672: Drop unneeded NULL checks

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After the commit 7735bce05a ("ASoC: Intel: boards: use devm_clk_get()
unconditionally") the driver assumes that mclk is always provided, hence
no need to check for it being NULL anymore.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20260428074758.3087437-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Andy Shevchenko 2026-04-28 09:47:58 +02:00 committed by Mark Brown
parent cda1cf0526
commit ee26bad1b5
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GPG Key ID: 24D68B725D5487D0
1 changed files with 24 additions and 32 deletions
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56
sound/soc/intel/boards/cht_bsw_rt5672.c
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@ -63,13 +63,11 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w,
}
if (SND_SOC_DAPM_EVENT_ON(event)) {
if (ctx->mclk) {
ret = clk_prepare_enable(ctx->mclk);
if (ret < 0) {
dev_err(card->dev,
"could not configure MCLK state: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(ctx->mclk);
if (ret < 0) {
dev_err(card->dev,
"could not configure MCLK state: %d\n", ret);
return ret;
}
/* set codec PLL source to the 19.2MHz platform clock (MCLK) */
@ -77,8 +75,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w,
CHT_PLAT_CLK_3_HZ, 48000 * 512);
if (ret < 0) {
dev_err(card->dev, "can't set codec pll: %d\n", ret);
if (ctx->mclk)
clk_disable_unprepare(ctx->mclk);
clk_disable_unprepare(ctx->mclk);
return ret;
}
@ -87,8 +84,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w,
48000 * 512, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
if (ctx->mclk)
clk_disable_unprepare(ctx->mclk);
clk_disable_unprepare(ctx->mclk);
return ret;
}
} else {
@ -104,8 +100,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w,
return ret;
}
if (ctx->mclk)
clk_disable_unprepare(ctx->mclk);
clk_disable_unprepare(ctx->mclk);
}
return 0;
}
@ -244,28 +239,25 @@ static int cht_codec_init(struct snd_soc_pcm_runtime *runtime)
snd_jack_set_key(ctx->headset.jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
rt5670_set_jack_detect(component, &ctx->headset);
if (ctx->mclk) {
/*
* The firmware might enable the clock at
* boot (this information may or may not
* be reflected in the enable clock register).
* To change the rate we must disable the clock
* first to cover these cases. Due to common
* clock framework restrictions that do not allow
* to disable a clock that has not been enabled,
* we need to enable the clock first.
*/
ret = clk_prepare_enable(ctx->mclk);
if (!ret)
clk_disable_unprepare(ctx->mclk);
ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
/*
* The firmware might enable the clock at boot (this information
* may or may not be reflected in the enable clock register).
* To change the rate we must disable the clock first to cover
* these cases. Due to Common Clock Framework restrictions that
* do not allow to disable a clock that has not been enabled, we
* need to enable the clock first.
*/
ret = clk_prepare_enable(ctx->mclk);
if (!ret)
clk_disable_unprepare(ctx->mclk);
if (ret) {
dev_err(runtime->dev, "unable to set MCLK rate\n");
return ret;
}
ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
if (ret) {
dev_err(runtime->dev, "unable to set MCLK rate\n");
return ret;
}
return 0;
}