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drm/amd/display: Avoid turning off the PHY when OTG is running for DVI

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[Why]
The OTG's virtual pixel clock source for DVI comes from the PHY.

If the signal type is DVI then the OTG can become stuck on pre DCN401
ASIC when DPMS off occurs because the OTG remains running but the
PHY transmitter is disabled.

[How]
There exists logic to keep track of the OTG running refcount on the
link to determine if the link needs to go to PLL_EN instead of TX_EN
but the logic only checks for HDMI TMDS on older ASIC.

DVI is still a TMDS signal type so the constraint should also apply.

Replace the checks for dc_is_hdmi_tmds_signal with dc_is_tmds_signal to
cover both HDMI and DVI for the symclk refcount workaround.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas 2026-03-13 16:25:25 -04:00 committed by Alex Deucher
parent a808615c2f
commit ee212b0208
4 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
View File

@ -1568,7 +1568,7 @@ static enum dc_status dce110_enable_stream_timing(
return DC_ERROR_UNEXPECTED;
}
if (dc_is_hdmi_tmds_signal(stream->signal)) {
if (dc_is_tmds_signal(stream->signal)) {
stream->link->phy_state.symclk_ref_cnts.otg = 1;
if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
@ -2418,7 +2418,7 @@ static void dce110_reset_hw_ctx_wrap(
BREAK_TO_DEBUGGER();
}
pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
if (dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal))
if (dc_is_tmds_signal(pipe_ctx_old->stream->signal))
pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);

4
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
View File

@ -893,7 +893,7 @@ enum dc_status dcn20_enable_stream_timing(
dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
}
if (dc_is_hdmi_tmds_signal(stream->signal)) {
if (dc_is_tmds_signal(stream->signal)) {
stream->link->phy_state.symclk_ref_cnts.otg = 1;
if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
@ -2856,7 +2856,7 @@ void dcn20_reset_back_end_for_pipe(
* the case where the same symclk is shared across multiple otg
* instances
*/
if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
if (dc_is_tmds_signal(pipe_ctx->stream->signal))
link->phy_state.symclk_ref_cnts.otg = 0;
if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
link_hwss->disable_link_output(link,

2
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
View File

@ -548,7 +548,7 @@ static void dcn31_reset_back_end_for_pipe(
* the case where the same symclk is shared across multiple otg
* instances
*/
if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
if (dc_is_tmds_signal(pipe_ctx->stream->signal))
link->phy_state.symclk_ref_cnts.otg = 0;
if (pipe_ctx->top_pipe == NULL) {

2
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
View File

@ -1938,7 +1938,7 @@ void dcn401_reset_back_end_for_pipe(
* the case where the same symclk is shared across multiple otg
* instances
*/
if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
if (dc_is_tmds_signal(pipe_ctx->stream->signal))
link->phy_state.symclk_ref_cnts.otg = 0;
if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
link_hwss->disable_link_output(link,