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net/mlx5: Add support for 200Gbps per lane link modes

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This patch exposes new link modes using 200Gbps per lane, including
200G, 400G and 800G modes.

Signed-off-by: Jianbo Liu <jianbol@nvidia.com>
Reviewed-by: Shahar Shitrit <shshitrit@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Jianbo Liu 2025-02-03 23:35:12 +02:00 committed by Paolo Abeni
parent 4897f9b7f8
commit ee0a4fc396
3 changed files with 27 additions and 0 deletions
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21
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
View File

@ -237,6 +237,27 @@ void mlx5e_build_ptys2ethtool_map(void)
ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT,
ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT,
ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT);
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_1_200GBASE_CR1_KR1, ext,
ETHTOOL_LINK_MODE_200000baseCR_Full_BIT,
ETHTOOL_LINK_MODE_200000baseKR_Full_BIT,
ETHTOOL_LINK_MODE_200000baseDR_Full_BIT,
ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT,
ETHTOOL_LINK_MODE_200000baseSR_Full_BIT,
ETHTOOL_LINK_MODE_200000baseVR_Full_BIT);
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_2_400GBASE_CR2_KR2, ext,
ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT,
ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT,
ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT,
ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT,
ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT,
ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT);
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_4_800GBASE_CR4_KR4, ext,
ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT,
ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT,
ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT,
ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT,
ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT,
ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT);
}
static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,

3
drivers/net/ethernet/mellanox/mlx5/core/port.c
View File

@ -1105,6 +1105,9 @@ static const u32 mlx5e_ext_link_speed[MLX5E_EXT_LINK_MODES_NUMBER] = {
[MLX5E_200GAUI_2_200GBASE_CR2_KR2] = 200000,
[MLX5E_400GAUI_4_400GBASE_CR4_KR4] = 400000,
[MLX5E_800GAUI_8_800GBASE_CR8_KR8] = 800000,
[MLX5E_200GAUI_1_200GBASE_CR1_KR1] = 200000,
[MLX5E_400GAUI_2_400GBASE_CR2_KR2] = 400000,
[MLX5E_800GAUI_4_800GBASE_CR4_KR4] = 800000,
};
int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,

3
include/linux/mlx5/port.h
View File

@ -115,9 +115,12 @@ enum mlx5e_ext_link_mode {
MLX5E_100GAUI_1_100GBASE_CR_KR = 11,
MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12,
MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13,
MLX5E_200GAUI_1_200GBASE_CR1_KR1 = 14,
MLX5E_400GAUI_8_400GBASE_CR8 = 15,
MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16,
MLX5E_400GAUI_2_400GBASE_CR2_KR2 = 17,
MLX5E_800GAUI_8_800GBASE_CR8_KR8 = 19,
MLX5E_800GAUI_4_800GBASE_CR4_KR4 = 20,
MLX5E_EXT_LINK_MODES_NUMBER,
};