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wifi: rtw89: 8922d: add set channel with pre-/post- helpers
The main set channel function calls MAC/BB/RF ones, and pre-/post- helpers are called before/after the main function to backup/restore and stop/restart circuits, including TX scheduler, PPDU status, DACK and TSSI. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260330065847.48946-3-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
parent
347fbc6027
commit
edf9f583c0
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@ -8445,6 +8445,8 @@
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#define RR_MOD_M_RXBB GENMASK(9, 5)
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#define RR_MOD_LO_SEL BIT(1)
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#define RR_MODOPT 0x01
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#define RR_MODOPT_V1 0x10001
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#define RR_SW_SEL BIT(19)
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#define RR_TXG_SEL GENMASK(19, 17)
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#define RR_MODOPT_M_TXPWR GENMASK(5, 0)
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#define RR_WLSEL 0x02
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@ -10527,6 +10529,8 @@
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#define R_TXPWR_RSTB0_BE4 0x2250C
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#define B_TXPWR_RSTB0_BE4 BIT(16)
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#define R_TSSI_EN_P0_BE4 0x22510
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#define B_TSSI_EN_P0_BE4 GENMASK(3, 0)
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#define R_TXPWR_RSTB1_BE4 0x2260C
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#define B_TXPWR_RSTB1_BE4 BIT(16)
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@ -10640,6 +10644,16 @@
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#define R_RX_PATH0_TBL0_BE4 0x2E028
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#define R_RX_PATH1_TBL0_BE4 0x2E128
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#define R_KTBL0A_BE4 0x38104
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#define R_KTBL0B_BE4 0x38204
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#define B_KTBL0_IDX0 GENMASK(1, 0)
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#define B_KTBL0_IDX1 GENMASK(9, 8)
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#define B_KTBL0_RST BIT(31)
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#define R_KTBL1A_BE4 0x38154
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#define R_KTBL1B_BE4 0x38254
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#define B_KTBL1_TBL0 BIT(3)
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#define B_KTBL1_TBL1 BIT(5)
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/* WiFi CPU local domain */
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#define R_AX_WDT_CTRL 0x0040
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#define B_AX_WDT_EN BIT(31)
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@ -2066,6 +2066,108 @@ static void rtw8922d_set_channel_bb(struct rtw89_dev *rtwdev,
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rtw8922d_tssi_reset(rtwdev, RF_PATH_AB, phy_idx);
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}
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static void rtw8922d_pre_set_channel_bb(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx)
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{
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if (!rtwdev->dbcc_en)
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return;
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rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4, B_SYS_DBCC_BE4, 0x0);
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if (phy_idx == RTW89_PHY_0) {
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xBBBB);
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fsleep(1);
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xAFFF);
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEBAD);
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fsleep(1);
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEAAD);
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} else {
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xBBBB);
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fsleep(1);
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xAFFF);
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fsleep(1);
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEFFF);
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEEFF);
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}
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fsleep(1);
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}
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static void rtw8922d_post_set_channel_bb(struct rtw89_dev *rtwdev,
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enum rtw89_mlo_dbcc_mode mode,
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enum rtw89_phy_idx phy_idx)
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{
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if (!rtwdev->dbcc_en)
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return;
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rtw8922d_ctrl_mlo(rtwdev, mode, true);
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}
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static void rtw8922d_set_channel(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_mac_idx mac_idx,
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enum rtw89_phy_idx phy_idx)
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{
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rtw8922d_set_channel_mac(rtwdev, chan, mac_idx);
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rtw8922d_set_channel_bb(rtwdev, chan, phy_idx);
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rtw8922d_set_channel_rf(rtwdev, chan, phy_idx);
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}
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static void __rtw8922d_dack_reset(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
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{
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rtw89_phy_write32_mask(rtwdev, 0x3c000 + (path << 8), BIT(17), 0x0);
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rtw89_phy_write32_mask(rtwdev, 0x3c000 + (path << 8), BIT(17), 0x1);
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}
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static void rtw8922d_dack_reset(struct rtw89_dev *rtwdev)
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{
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__rtw8922d_dack_reset(rtwdev, RF_PATH_A);
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__rtw8922d_dack_reset(rtwdev, RF_PATH_B);
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}
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static
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void rtw8922d_hal_reset(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx, enum rtw89_mac_idx mac_idx,
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enum rtw89_band band, u32 *tx_en, bool enter)
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{
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if (enter) {
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rtw89_chip_stop_sch_tx(rtwdev, mac_idx, tx_en, RTW89_SCH_TX_SEL_ALL);
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rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
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rtw8922d_dack_reset(rtwdev);
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rtw8922d_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
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fsleep(40);
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rtw8922d_bb_reset_en(rtwdev, band, false, phy_idx);
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} else {
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rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
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rtw8922d_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
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rtw8922d_bb_reset_en(rtwdev, band, true, phy_idx);
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rtw89_chip_resume_sch_tx(rtwdev, mac_idx, *tx_en);
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}
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}
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static void rtw8922d_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
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struct rtw89_channel_help_params *p,
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const struct rtw89_chan *chan,
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enum rtw89_mac_idx mac_idx,
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enum rtw89_phy_idx phy_idx)
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{
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if (enter) {
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rtw8922d_pre_set_channel_bb(rtwdev, phy_idx);
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rtw8922d_pre_set_channel_rf(rtwdev, phy_idx);
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}
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rtw8922d_hal_reset(rtwdev, phy_idx, mac_idx, chan->band_type, &p->tx_en, enter);
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if (!enter) {
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rtw8922d_post_set_channel_bb(rtwdev, rtwdev->mlo_dbcc_mode, phy_idx);
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rtw8922d_post_set_channel_rf(rtwdev, phy_idx);
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}
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}
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MODULE_FIRMWARE(RTW8922D_MODULE_FIRMWARE);
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MODULE_FIRMWARE(RTW8922DS_MODULE_FIRMWARE);
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MODULE_AUTHOR("Realtek Corporation");
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@ -2,11 +2,40 @@
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/* Copyright(c) 2026 Realtek Corporation
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*/
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#include "chan.h"
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#include "debug.h"
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#include "phy.h"
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#include "reg.h"
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#include "rtw8922d.h"
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#include "rtw8922d_rfk.h"
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static void rtw8922d_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
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enum rtw89_rf_path path, u8 phy_idx)
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{
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static const u32 tssi_trk_man[2] = {R_TSSI_EN_P0_BE4,
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R_TSSI_EN_P0_BE4 + 0x100};
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if (en)
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rtw89_phy_write32_idx(rtwdev, tssi_trk_man[path],
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B_TSSI_CONT_EN, 0, phy_idx);
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else
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rtw89_phy_write32_idx(rtwdev, tssi_trk_man[path],
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B_TSSI_CONT_EN, 1, phy_idx);
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}
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void rtw8922d_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx)
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{
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if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
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if (phy_idx == RTW89_PHY_0)
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rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_A, phy_idx);
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else
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rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_B, phy_idx);
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} else {
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rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_A, phy_idx);
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rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_B, phy_idx);
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}
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}
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static
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void rtw8922d_ctl_band_ch_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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const struct rtw89_chan *chan)
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@ -31,3 +60,204 @@ void rtw8922d_set_channel_rf(struct rtw89_dev *rtwdev,
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{
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rtw8922d_ctl_band_ch_bw(rtwdev, phy_idx, chan);
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}
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enum _rf_syn_pow {
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RF_SYN_ON_OFF,
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RF_SYN_OFF_ON,
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RF_SYN_ALLON,
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RF_SYN_ALLOFF,
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};
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static void rtw8922d_set_syn01(struct rtw89_dev *rtwdev, enum _rf_syn_pow syn)
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{
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "SYN config=%d\n", syn);
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if (syn == RF_SYN_ALLON) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, BIT(1), 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, BIT(1), 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0xf);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0xf);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x1);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x1);
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} else if (syn == RF_SYN_ON_OFF) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, BIT(1), 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0xf);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x1);
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} else if (syn == RF_SYN_OFF_ON) {
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, BIT(1), 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0xf);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x1);
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} else if (syn == RF_SYN_ALLOFF) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0x0);
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}
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}
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static void rtw8922d_chlk_ktbl_sel(struct rtw89_dev *rtwdev, u8 kpath, u8 idx)
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{
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bool mlo_linking = false;
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if (idx > 2) {
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rtw89_warn(rtwdev, "[DBCC][ERROR]indx is out of limit!! index(%d)", idx);
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return;
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}
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if (mlo_linking) {
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if (kpath & RF_A) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_SW_SEL, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT_V1, RR_SW_SEL, 0x0);
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}
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if (kpath & RF_B) {
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_SW_SEL, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT_V1, RR_SW_SEL, 0x0);
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}
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return;
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}
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if (kpath & RF_A) {
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rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_RST, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_IDX0, idx);
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rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_IDX1, idx);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_TXG_SEL, 0x4 | idx);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT_V1, RR_TXG_SEL, 0x4 | idx);
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rtw89_phy_write32_mask(rtwdev, R_KTBL1A_BE4, B_KTBL1_TBL0, idx & BIT(0));
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rtw89_phy_write32_mask(rtwdev, R_KTBL1A_BE4, B_KTBL1_TBL1, (idx & BIT(1)) >> 1);
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}
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if (kpath & RF_B) {
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rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_RST, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_IDX0, idx);
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rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_IDX1, idx);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_TXG_SEL, 0x4 | idx);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT_V1, RR_TXG_SEL, 0x4 | idx);
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rtw89_phy_write32_mask(rtwdev, R_KTBL1B_BE4, B_KTBL1_TBL0, idx & BIT(0));
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rtw89_phy_write32_mask(rtwdev, R_KTBL1B_BE4, B_KTBL1_TBL1, (idx & BIT(1)) >> 1);
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}
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}
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static u8 rtw8922d_chlk_reload_sel_tbl(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan, u8 path)
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{
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struct rtw89_rfk_mcc_info_data *rfk_mcc = rtwdev->rfk_mcc.data;
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struct rtw89_rfk_chan_desc desc[__RTW89_RFK_CHS_NR_V1] = {};
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u8 tbl_sel;
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for (tbl_sel = 0; tbl_sel < ARRAY_SIZE(desc); tbl_sel++) {
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struct rtw89_rfk_chan_desc *p = &desc[tbl_sel];
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p->ch = rfk_mcc->ch[tbl_sel];
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p->has_band = true;
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p->band = rfk_mcc->band[tbl_sel];
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p->has_bw = true;
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p->bw = rfk_mcc->bw[tbl_sel];
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}
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tbl_sel = rtw89_rfk_chan_lookup(rtwdev, desc, ARRAY_SIZE(desc), chan);
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rfk_mcc->ch[tbl_sel] = chan->channel;
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rfk_mcc->band[tbl_sel] = chan->band_type;
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rfk_mcc->bw[tbl_sel] = chan->band_width;
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rfk_mcc->rf18[tbl_sel] = rtw89_chip_chan_to_rf18_val(rtwdev, chan);
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/* shared table array, but tbl_sel can be independent by path */
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rfk_mcc[path].table_idx = tbl_sel;
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return tbl_sel;
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}
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static void rtw8922d_chlk_reload(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_chan *chan0, *chan1;
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u8 s0_tbl, s1_tbl;
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switch (rtwdev->mlo_dbcc_mode) {
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default:
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case MLO_2_PLUS_0_1RF:
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chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
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chan1 = chan0;
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break;
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case MLO_0_PLUS_2_1RF:
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chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
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chan0 = chan1;
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break;
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case MLO_1_PLUS_1_1RF:
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chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
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chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
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break;
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}
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s0_tbl = rtw8922d_chlk_reload_sel_tbl(rtwdev, chan0, 0);
|
||||
s1_tbl = rtw8922d_chlk_reload_sel_tbl(rtwdev, chan1, 1);
|
||||
|
||||
rtw8922d_chlk_ktbl_sel(rtwdev, RF_A, s0_tbl);
|
||||
rtw8922d_chlk_ktbl_sel(rtwdev, RF_B, s1_tbl);
|
||||
}
|
||||
|
||||
static enum _rf_syn_pow rtw8922d_get_syn_pow(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
switch (rtwdev->mlo_dbcc_mode) {
|
||||
case MLO_0_PLUS_2_1RF:
|
||||
return RF_SYN_OFF_ON;
|
||||
case MLO_0_PLUS_2_2RF:
|
||||
case MLO_1_PLUS_1_2RF:
|
||||
case MLO_2_PLUS_0_1RF:
|
||||
case MLO_2_PLUS_0_2RF:
|
||||
case MLO_2_PLUS_2_2RF:
|
||||
case MLO_DBCC_NOT_SUPPORT:
|
||||
default:
|
||||
return RF_SYN_ON_OFF;
|
||||
case MLO_1_PLUS_1_1RF:
|
||||
case DBCC_LEGACY:
|
||||
return RF_SYN_ALLON;
|
||||
}
|
||||
}
|
||||
|
||||
void rtw8922d_rfk_mlo_ctrl(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
enum _rf_syn_pow syn_pow = rtw8922d_get_syn_pow(rtwdev);
|
||||
|
||||
if (!rtwdev->dbcc_en)
|
||||
goto set_rfk_reload;
|
||||
|
||||
rtw8922d_set_syn01(rtwdev, syn_pow);
|
||||
|
||||
set_rfk_reload:
|
||||
rtw8922d_chlk_reload(rtwdev);
|
||||
}
|
||||
|
||||
void rtw8922d_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
|
||||
{
|
||||
bool mlo_1_1;
|
||||
|
||||
if (!rtwdev->dbcc_en)
|
||||
return;
|
||||
|
||||
mlo_1_1 = rtw89_is_mlo_1_1(rtwdev);
|
||||
if (mlo_1_1)
|
||||
rtw8922d_set_syn01(rtwdev, RF_SYN_ALLON);
|
||||
else if (phy_idx == RTW89_PHY_0)
|
||||
rtw8922d_set_syn01(rtwdev, RF_SYN_ON_OFF);
|
||||
else
|
||||
rtw8922d_set_syn01(rtwdev, RF_SYN_OFF_ON);
|
||||
|
||||
fsleep(1000);
|
||||
}
|
||||
|
||||
void rtw8922d_post_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
|
||||
{
|
||||
rtw8922d_rfk_mlo_ctrl(rtwdev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,8 +7,12 @@
|
|||
|
||||
#include "core.h"
|
||||
|
||||
void rtw8922d_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx);
|
||||
void rtw8922d_set_channel_rf(struct rtw89_dev *rtwdev,
|
||||
const struct rtw89_chan *chan,
|
||||
enum rtw89_phy_idx phy_idx);
|
||||
void rtw8922d_rfk_mlo_ctrl(struct rtw89_dev *rtwdev);
|
||||
void rtw8922d_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
|
||||
void rtw8922d_post_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user