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UPSTREAM: KVM: arm64: CSSELR_EL1 max is 13

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Not counting TnD, which KVM doesn't currently consider, CSSELR_EL1
can have a maximum value of 0b1101 (13), which corresponds to an
instruction cache at level 7. With CSSELR_MAX set to 12 we can
only select up to cache level 6. Change it to 14.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20201126134641.35231-2-drjones@redhat.com
(cherry picked from commit c73a441617)
Signed-off-by: Will Deacon <willdeacon@google.com>
Change-Id: I3030c34b51fc7e596d723fe071459a3719924455
Bug: 178098380
Test: atest VirtualizationHostTestCases on an EL2-enabled device
This commit is contained in:
Andrew Jones 2020-11-26 14:46:40 +01:00 committed by Will Deacon
parent 420469a74d
commit ed6a6eb7ec
1 changed files with 1 additions and 1 deletions
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2
arch/arm64/kvm/sys_regs.c
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@ -87,7 +87,7 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
static u32 cache_levels;
/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
#define CSSELR_MAX 12
#define CSSELR_MAX 14
/* Which cache CCSIDR represents depends on CSSELR value. */
static u32 get_ccsidr(u32 csselr)