From 22c8ce0aa274cea2ff538ffdf723053ecf77d78b Mon Sep 17 00:00:00 2001 From: Sai Krishna Potthuri Date: Mon, 20 Mar 2023 15:29:30 +0530 Subject: [PATCH 1/2] spi: cadence-quadspi: Update the read timeout based on the length When performing indirect read via external DMA the timeout for completion is set equal to the read length instead of fixed timeout value. For reads larger than 500 bytes, the timeout will continue to be equal to the read length whereas for a small read like the Read Status Register command, the timeout would be 1 or 2 milliseconds. This is not enough to cover the overhead needed in setting up DMA, in that case make sure the timeout is at least 500ms to allow DMA to finish. This solution is inline with the timeout used for Direct read via DMA. Signed-off-by: Sai Krishna Potthuri Link: https://lore.kernel.org/r/20230320095931.2651714-2-sai.krishna.potthuri@amd.com Signed-off-by: Mark Brown --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 79ab7e309644..e281732aba91 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -863,7 +863,7 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); if (!wait_for_completion_timeout(&cqspi->transfer_complete, - msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { + msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { ret = -ETIMEDOUT; goto failrd; } From c0b53f4e545e4c6106aab553eb351138d46211cc Mon Sep 17 00:00:00 2001 From: Sai Krishna Potthuri Date: Mon, 20 Mar 2023 15:29:31 +0530 Subject: [PATCH 2/2] spi: cadence-quadspi: Disable the SPI before reconfiguring Observed random DMA timeout failures while doing back to back transfers which involves switching the modes from DMA to NON-DMA. This issue is observed while testing the OSPI+UBIFS file system test case where rootfs is mounted from OSPI UBIFS partition. To avoid this issue, disable the SPI before changing the configuration from external DMA to NON-DMA and vice versa and reenable it after changing the configuration. As per the Cadence Octal SPI design specification, it is recommended to disable the Octal-SPI enable bit before reconfiguring. Signed-off-by: Sai Krishna Potthuri Link: https://lore.kernel.org/r/20230320095931.2651714-3-sai.krishna.potthuri@amd.com Signed-off-by: Mark Brown --- drivers/spi/spi-cadence-quadspi.c | 38 +++++++++++++++++++------------ 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index e281732aba91..d4a2b72985da 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -791,6 +791,21 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, return ret; } +static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) +{ + void __iomem *reg_base = cqspi->iobase; + unsigned int reg; + + reg = readl(reg_base + CQSPI_REG_CONFIG); + + if (enable) + reg |= CQSPI_REG_CONFIG_ENABLE_MASK; + else + reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; + + writel(reg, reg_base + CQSPI_REG_CONFIG); +} + static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx) @@ -815,10 +830,14 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, if (ret) return ret; + cqspi_controller_enable(cqspi, 0); + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); reg |= CQSPI_REG_CONFIG_DMA_MASK; writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + cqspi_controller_enable(cqspi, 1); + dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); if (dma_mapping_error(dev, dma_addr)) { dev_err(dev, "dma mapping failed\n"); @@ -876,10 +895,14 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, cqspi->iobase + CQSPI_REG_INDIRECTRD); dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); + cqspi_controller_enable(cqspi, 0); + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); reg &= ~CQSPI_REG_CONFIG_DMA_MASK; writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + cqspi_controller_enable(cqspi, 1); + ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); if (ret) @@ -1182,21 +1205,6 @@ static void cqspi_readdata_capture(struct cqspi_st *cqspi, writel(reg, reg_base + CQSPI_REG_READCAPTURE); } -static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) -{ - void __iomem *reg_base = cqspi->iobase; - unsigned int reg; - - reg = readl(reg_base + CQSPI_REG_CONFIG); - - if (enable) - reg |= CQSPI_REG_CONFIG_ENABLE_MASK; - else - reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; - - writel(reg, reg_base + CQSPI_REG_CONFIG); -} - static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, unsigned long sclk) {