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x86/ioapic: Use guard() for locking where applicable
KISS rules! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Tested-by: Breno Leitao <leitao@debian.org> Link: https://lore.kernel.org/all/20240802155440.464227224@linutronix.de
This commit is contained in:
Thomas Gleixner
parent
d8c76d0167
commit
ed57538b85
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@ -296,14 +296,8 @@ static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
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static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
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{
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struct IO_APIC_route_entry entry;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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entry = __ioapic_read_entry(apic, pin);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return entry;
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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return __ioapic_read_entry(apic, pin);
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}
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/*
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@ -320,11 +314,8 @@ static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e
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static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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__ioapic_write_entry(apic, pin, e);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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/*
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@ -335,12 +326,10 @@ static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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static void ioapic_mask_entry(int apic, int pin)
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{
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struct IO_APIC_route_entry e = { .masked = true };
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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io_apic_write(apic, 0x10 + 2*pin, e.w1);
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io_apic_write(apic, 0x11 + 2*pin, e.w2);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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/*
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@ -433,11 +422,9 @@ static void io_apic_sync(struct irq_pin_list *entry)
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static void mask_ioapic_irq(struct irq_data *irq_data)
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{
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struct mp_chip_data *data = irq_data->chip_data;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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io_apic_modify_irq(data, true, &io_apic_sync);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void __unmask_ioapic(struct mp_chip_data *data)
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@ -448,11 +435,9 @@ static void __unmask_ioapic(struct mp_chip_data *data)
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static void unmask_ioapic_irq(struct irq_data *irq_data)
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{
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struct mp_chip_data *data = irq_data->chip_data;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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__unmask_ioapic(data);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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/*
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@ -497,13 +482,11 @@ static void __eoi_ioapic_pin(int apic, int pin, int vector)
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static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
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{
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unsigned long flags;
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struct irq_pin_list *entry;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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for_each_irq_pin(entry, data->irq_2_pin)
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__eoi_ioapic_pin(entry->apic, entry->pin, vector);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
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@ -526,8 +509,6 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
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}
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if (entry.irr) {
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unsigned long flags;
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/*
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* Make sure the trigger mode is set to level. Explicit EOI
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* doesn't clear the remote-IRR if the trigger mode is not
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@ -537,9 +518,8 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
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entry.is_level = true;
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ioapic_write_entry(apic, pin, entry);
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}
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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__eoi_ioapic_pin(apic, pin, entry.vector);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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/*
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@ -1033,7 +1013,7 @@ static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
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return -EINVAL;
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}
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mutex_lock(&ioapic_mutex);
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guard(mutex)(&ioapic_mutex);
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if (!(flags & IOAPIC_MAP_ALLOC)) {
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if (!legacy) {
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irq = irq_find_mapping(domain, pin);
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@ -1054,8 +1034,6 @@ static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
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data->count++;
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}
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}
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mutex_unlock(&ioapic_mutex);
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return irq;
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}
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@ -1120,10 +1098,9 @@ void mp_unmap_irq(int irq)
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if (!data || data->isa_irq)
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return;
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mutex_lock(&ioapic_mutex);
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guard(mutex)(&ioapic_mutex);
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if (--data->count == 0)
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irq_domain_free_irqs(irq, 1);
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mutex_unlock(&ioapic_mutex);
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}
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/*
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@ -1251,16 +1228,15 @@ static void __init print_IO_APIC(int ioapic_idx)
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union IO_APIC_reg_01 reg_01;
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union IO_APIC_reg_02 reg_02;
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union IO_APIC_reg_03 reg_03;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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reg_00.raw = io_apic_read(ioapic_idx, 0);
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reg_01.raw = io_apic_read(ioapic_idx, 1);
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if (reg_01.bits.version >= 0x10)
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reg_02.raw = io_apic_read(ioapic_idx, 2);
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if (reg_01.bits.version >= 0x20)
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reg_03.raw = io_apic_read(ioapic_idx, 3);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
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reg_00.raw = io_apic_read(ioapic_idx, 0);
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reg_01.raw = io_apic_read(ioapic_idx, 1);
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if (reg_01.bits.version >= 0x10)
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reg_02.raw = io_apic_read(ioapic_idx, 2);
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if (reg_01.bits.version >= 0x20)
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reg_03.raw = io_apic_read(ioapic_idx, 3);
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}
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printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
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printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
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@ -1451,7 +1427,6 @@ static void __init setup_ioapic_ids_from_mpc_nocheck(void)
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const u32 broadcast_id = 0xF;
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union IO_APIC_reg_00 reg_00;
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unsigned char old_id;
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unsigned long flags;
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int ioapic_idx, i;
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/*
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@ -1465,9 +1440,8 @@ static void __init setup_ioapic_ids_from_mpc_nocheck(void)
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*/
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for_each_ioapic(ioapic_idx) {
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/* Read the register 0 value */
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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reg_00.raw = io_apic_read(ioapic_idx, 0);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
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reg_00.raw = io_apic_read(ioapic_idx, 0);
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old_id = mpc_ioapic_id(ioapic_idx);
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@ -1522,16 +1496,11 @@ static void __init setup_ioapic_ids_from_mpc_nocheck(void)
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mpc_ioapic_id(ioapic_idx));
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reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(ioapic_idx, 0, reg_00.raw);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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/*
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* Sanity check
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*/
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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reg_00.raw = io_apic_read(ioapic_idx, 0);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
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io_apic_write(ioapic_idx, 0, reg_00.raw);
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reg_00.raw = io_apic_read(ioapic_idx, 0);
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}
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/* Sanity check */
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if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
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pr_cont("could not set ID!\n");
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else
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@ -1661,17 +1630,14 @@ static int __init timer_irq_works(void)
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static unsigned int startup_ioapic_irq(struct irq_data *data)
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{
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int was_pending = 0, irq = data->irq;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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if (irq < nr_legacy_irqs()) {
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legacy_pic->mask(irq);
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if (legacy_pic->irq_pending(irq))
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was_pending = 1;
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}
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__unmask_ioapic(data->chip_data);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return was_pending;
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}
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@ -1681,9 +1647,8 @@ atomic_t irq_mis_count;
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static bool io_apic_level_ack_pending(struct mp_chip_data *data)
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{
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struct irq_pin_list *entry;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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for_each_irq_pin(entry, data->irq_2_pin) {
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struct IO_APIC_route_entry e;
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int pin;
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@ -1691,13 +1656,9 @@ static bool io_apic_level_ack_pending(struct mp_chip_data *data)
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pin = entry->pin;
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e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);
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/* Is the remote IRR bit set? */
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if (e.irr) {
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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if (e.irr)
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return true;
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}
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}
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return false;
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}
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@ -1898,18 +1859,16 @@ static void ioapic_configure_entry(struct irq_data *irqd)
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__ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
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}
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static int ioapic_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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static int ioapic_set_affinity(struct irq_data *irq_data, const struct cpumask *mask, bool force)
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{
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struct irq_data *parent = irq_data->parent_data;
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unsigned long flags;
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int ret;
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ret = parent->chip->irq_set_affinity(parent, mask, force);
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
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ioapic_configure_entry(irq_data);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return ret;
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}
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@ -1928,9 +1887,8 @@ static int ioapic_set_affinity(struct irq_data *irq_data,
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*
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* Verify that the corresponding Remote-IRR bits are clear.
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*/
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static int ioapic_irq_get_chip_state(struct irq_data *irqd,
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enum irqchip_irq_state which,
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bool *state)
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static int ioapic_irq_get_chip_state(struct irq_data *irqd, enum irqchip_irq_state which,
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bool *state)
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{
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struct mp_chip_data *mcd = irqd->chip_data;
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struct IO_APIC_route_entry rentry;
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@ -1940,7 +1898,8 @@ static int ioapic_irq_get_chip_state(struct irq_data *irqd,
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return -EINVAL;
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*state = false;
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raw_spin_lock(&ioapic_lock);
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guard(raw_spinlock)(&ioapic_lock);
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for_each_irq_pin(p, mcd->irq_2_pin) {
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rentry = __ioapic_read_entry(p->apic, p->pin);
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/*
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@ -1954,7 +1913,6 @@ static int ioapic_irq_get_chip_state(struct irq_data *irqd,
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break;
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}
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}
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raw_spin_unlock(&ioapic_lock);
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return 0;
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}
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@ -2129,9 +2087,8 @@ static int __init mp_alloc_timer_irq(int ioapic, int pin)
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ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
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info.devid = mpc_ioapic_id(ioapic);
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info.ioapic.pin = pin;
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mutex_lock(&ioapic_mutex);
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guard(mutex)(&ioapic_mutex);
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irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
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mutex_unlock(&ioapic_mutex);
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}
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return irq;
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@ -2142,8 +2099,6 @@ static int __init mp_alloc_timer_irq(int ioapic, int pin)
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* a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
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* is so screwy. Thanks to Brian Perkins for testing/hacking this beast
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* fanatically on his truly buggy board.
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*
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* FIXME: really need to revamp this for all platforms.
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*/
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static inline void __init check_timer(void)
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{
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@ -2404,16 +2359,14 @@ void __init setup_IO_APIC(void)
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static void resume_ioapic_id(int ioapic_idx)
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{
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unsigned long flags;
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union IO_APIC_reg_00 reg_00;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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reg_00.raw = io_apic_read(ioapic_idx, 0);
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if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
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reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
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io_apic_write(ioapic_idx, 0, reg_00.raw);
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}
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void ioapic_resume(void)
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@ -2443,15 +2396,13 @@ device_initcall(ioapic_init_ops);
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static int io_apic_get_redir_entries(int ioapic)
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{
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union IO_APIC_reg_01 reg_01;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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guard(raw_spinlock_irqsave)(&ioapic_lock);
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reg_01.raw = io_apic_read(ioapic, 1);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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/* The register returns the maximum index redir index
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* supported, which is one less than the total number of redir
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* entries.
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/*
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* The register returns the maximum index redir index supported,
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* which is one less than the total number of redir entries.
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*/
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return reg_01.bits.entries + 1;
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}
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@ -2481,16 +2432,14 @@ static int io_apic_get_unique_id(int ioapic, int apic_id)
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static DECLARE_BITMAP(apic_id_map, MAX_LOCAL_APIC);
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const u32 broadcast_id = 0xF;
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union IO_APIC_reg_00 reg_00;
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unsigned long flags;
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int i = 0;
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/* Initialize the ID map */
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if (bitmap_empty(apic_id_map, MAX_LOCAL_APIC))
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copy_phys_cpu_present_map(apic_id_map);
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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reg_00.raw = io_apic_read(ioapic, 0);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
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reg_00.raw = io_apic_read(ioapic, 0);
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if (apic_id >= broadcast_id) {
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pr_warn("IOAPIC[%d]: Invalid apic_id %d, trying %d\n",
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@ -2517,21 +2466,19 @@ static int io_apic_get_unique_id(int ioapic, int apic_id)
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if (reg_00.bits.ID != apic_id) {
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reg_00.bits.ID = apic_id;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(ioapic, 0, reg_00.raw);
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reg_00.raw = io_apic_read(ioapic, 0);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
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io_apic_write(ioapic, 0, reg_00.raw);
|
||||
reg_00.raw = io_apic_read(ioapic, 0);
|
||||
}
|
||||
|
||||
/* Sanity check */
|
||||
if (reg_00.bits.ID != apic_id) {
|
||||
pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
|
||||
ioapic);
|
||||
pr_err("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
apic_printk(APIC_VERBOSE, KERN_INFO
|
||||
"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
|
||||
apic_printk(APIC_VERBOSE, KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
|
||||
|
||||
return apic_id;
|
||||
}
|
||||
|
|
@ -2547,7 +2494,6 @@ static u8 io_apic_unique_id(int idx, u8 id)
|
|||
{
|
||||
union IO_APIC_reg_00 reg_00;
|
||||
DECLARE_BITMAP(used, 256);
|
||||
unsigned long flags;
|
||||
u8 new_id;
|
||||
int i;
|
||||
|
||||
|
|
@ -2563,26 +2509,23 @@ static u8 io_apic_unique_id(int idx, u8 id)
|
|||
* Read the current id from the ioapic and keep it if
|
||||
* available.
|
||||
*/
|
||||
raw_spin_lock_irqsave(&ioapic_lock, flags);
|
||||
reg_00.raw = io_apic_read(idx, 0);
|
||||
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
|
||||
scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
|
||||
reg_00.raw = io_apic_read(idx, 0);
|
||||
|
||||
new_id = reg_00.bits.ID;
|
||||
if (!test_bit(new_id, used)) {
|
||||
apic_printk(APIC_VERBOSE, KERN_INFO
|
||||
"IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
|
||||
idx, new_id, id);
|
||||
apic_printk(APIC_VERBOSE, KERN_INFO "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
|
||||
idx, new_id, id);
|
||||
return new_id;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the next free id and write it to the ioapic.
|
||||
*/
|
||||
/* Get the next free id and write it to the ioapic. */
|
||||
new_id = find_first_zero_bit(used, 256);
|
||||
reg_00.bits.ID = new_id;
|
||||
raw_spin_lock_irqsave(&ioapic_lock, flags);
|
||||
io_apic_write(idx, 0, reg_00.raw);
|
||||
reg_00.raw = io_apic_read(idx, 0);
|
||||
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
|
||||
scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
|
||||
io_apic_write(idx, 0, reg_00.raw);
|
||||
reg_00.raw = io_apic_read(idx, 0);
|
||||
}
|
||||
/* Sanity check */
|
||||
BUG_ON(reg_00.bits.ID != new_id);
|
||||
|
||||
|
|
@ -2592,12 +2535,10 @@ static u8 io_apic_unique_id(int idx, u8 id)
|
|||
|
||||
static int io_apic_get_version(int ioapic)
|
||||
{
|
||||
union IO_APIC_reg_01 reg_01;
|
||||
unsigned long flags;
|
||||
union IO_APIC_reg_01 reg_01;
|
||||
|
||||
raw_spin_lock_irqsave(&ioapic_lock, flags);
|
||||
guard(raw_spinlock_irqsave)(&ioapic_lock);
|
||||
reg_01.raw = io_apic_read(ioapic, 1);
|
||||
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
|
||||
|
||||
return reg_01.bits.version;
|
||||
}
|
||||
|
|
@ -3050,22 +2991,17 @@ void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
|
|||
irq_data = irq_domain_get_irq_data(domain, virq);
|
||||
if (irq_data && irq_data->chip_data) {
|
||||
data = irq_data->chip_data;
|
||||
__remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
|
||||
(int)irq_data->hwirq);
|
||||
__remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq);
|
||||
WARN_ON(!list_empty(&data->irq_2_pin));
|
||||
kfree(irq_data->chip_data);
|
||||
}
|
||||
irq_domain_free_irqs_top(domain, virq, nr_irqs);
|
||||
}
|
||||
|
||||
int mp_irqdomain_activate(struct irq_domain *domain,
|
||||
struct irq_data *irq_data, bool reserve)
|
||||
int mp_irqdomain_activate(struct irq_domain *domain, struct irq_data *irq_data, bool reserve)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&ioapic_lock, flags);
|
||||
guard(raw_spinlock_irqsave)(&ioapic_lock);
|
||||
ioapic_configure_entry(irq_data);
|
||||
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user