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spi: spi-qpic-snand: Increase ECC strength for large OOB SPI-NAND devices

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Some SPI-NAND devices with large OOB areas require a stronger ECC
configuration than the default one provided through firmware
description. For example, Macronix devices with a 256-byte OOB area
report that 4-bit ECC is insufficient and trigger:

  nand: WARNING: the ECC used on your system is too weak compared
  to the one required by the NAND chip

The QPIC SPI-NAND controller supports both 4-bit and 8-bit BCH ECC
modes. When a device exposes an OOB area of at least 128 bytes, there
is sufficient space to accommodate 8-bit ECC without exceeding the OOB
layout constraints.

Automatically increase the ECC strength to 8 bits when the detected OOB
size is 128 bytes or larger and the current configuration requests a
weaker ECC level. This avoids ECC capability mismatches on devices that
require stronger error correction and improves reliability.

Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260716-8bitecc-v1-1-6eef4bcc3a14@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Md Sadre Alam 2026-07-16 11:13:05 +05:30 committed by Mark Brown
parent a44a020465
commit ed4b52b24c
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1 changed files with 13 additions and 0 deletions
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13
drivers/spi/spi-qpic-snand.c
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@ -274,6 +274,19 @@ static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
ecc_cfg->strength = 4;
}
/*
* Override ECC strength based on OOB size to avoid weak ECC warning.
* If OOB size is more than 128 bytes, use 8-bit ECC for better
* error correction capability, which is required by chips with
* larger OOB areas like Macronix SPI NAND with 256 bytes OOB.
*/
if (mtd->oobsize >= 128 && ecc_cfg->strength < 8) {
dev_info(snandc->dev,
"Upgrading ECC strength from %d to 8 bits (OOB size: %d bytes)\n",
ecc_cfg->strength, mtd->oobsize);
ecc_cfg->strength = 8;
}
if (ecc_cfg->step_size != NANDC_STEP_SIZE) {
dev_err(snandc->dev,
"only %u bytes ECC step size is supported\n",