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Merge patch series "upboard pinctrl support for device id INTC1055"

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Gary Wang <is0124@gmail.com> says:

Add missing groups and functions in Tigerlake's pinctrl driver for INTC1055.
Add support "UP Xtreme i12" board.

The pinctrl-upboard is provide additional driving power & pin mux function
through native SOC pins->FPGA/CPLD->hat pins for flexable board level
applications. it's probe from ACPI device id AANT0F01 & AANT0F04.

Link: https://patch.msgid.link/20260706-upboard-pinctrl-add-upboard-intc1055-support-v4-0-cedce0802d3d@gmail.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This commit is contained in:
Andy Shevchenko 2026-07-08 16:28:13 +02:00
commit ed1608d5e3
2 changed files with 53 additions and 0 deletions
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32
drivers/pinctrl/intel/pinctrl-tigerlake.c
View File

@ -330,6 +330,34 @@ static const struct pinctrl_pin_desc tgllp_pins[] = {
PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"),
};
static const unsigned int tgllp_i2c0_pins[] = { 5, 6 };
static const unsigned int tgllp_i2c1_pins[] = { 7, 8 };
static const unsigned int tgllp_pwm0_pins[] = { 99 };
static const unsigned int tgllp_uart1_pins[] = { 85, 86, 87, 88 };
static const unsigned int tgllp_ssp2_pins[] = { 108, 109, 110, 111 };
static const struct intel_pingroup tgllp_groups[] = {
PIN_GROUP("i2c0_grp", tgllp_i2c0_pins, 2),
PIN_GROUP("i2c1_grp", tgllp_i2c1_pins, 2),
PIN_GROUP("pwm0_grp", tgllp_pwm0_pins, 2),
PIN_GROUP("uart1_grp", tgllp_uart1_pins, 2),
PIN_GROUP("ssp2_grp", tgllp_ssp2_pins, 7),
};
static const char * const tgllp_i2c0_groups[] = { "i2c0_grp" };
static const char * const tgllp_i2c1_groups[] = { "i2c1_grp" };
static const char * const tgllp_pwm0_groups[] = { "pwm0_grp" };
static const char * const tgllp_uart1_groups[] = { "uart1_grp" };
static const char * const tgllp_ssp2_groups[] = { "ssp2_grp" };
static const struct intel_function tgllp_functions[] = {
FUNCTION("i2c0", tgllp_i2c0_groups),
FUNCTION("i2c1", tgllp_i2c1_groups),
FUNCTION("pwm0", tgllp_pwm0_groups),
FUNCTION("uart1", tgllp_uart1_groups),
FUNCTION("ssp2", tgllp_ssp2_groups),
};
static const struct intel_padgroup tgllp_community0_gpps[] = {
INTEL_GPP(0, 0, 25, 0), /* GPP_B */
INTEL_GPP(1, 26, 41, 32), /* GPP_T */
@ -367,6 +395,10 @@ static const struct intel_community tgllp_communities[] = {
static const struct intel_pinctrl_soc_data tgllp_soc_data = {
.pins = tgllp_pins,
.npins = ARRAY_SIZE(tgllp_pins),
.groups = tgllp_groups,
.ngroups = ARRAY_SIZE(tgllp_groups),
.functions = tgllp_functions,
.nfunctions = ARRAY_SIZE(tgllp_functions),
.communities = tgllp_communities,
.ncommunities = ARRAY_SIZE(tgllp_communities),
};

21
drivers/pinctrl/pinctrl-upboard.c
View File

@ -912,6 +912,19 @@ static const struct upboard_pinctrl_map upboard_pinctrl_map_apl01 = {
.nmaps = ARRAY_SIZE(pinctrl_map_apl01),
};
static const struct pinctrl_map pinctrl_map_adl[] = {
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "i2c0_grp", "i2c0"),
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "i2c1_grp", "i2c1"),
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "pwm0_grp", "pwm0"),
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "uart1_grp", "uart1"),
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "ssp2_grp", "ssp2"),
};
static const struct upboard_pinctrl_map upboard_pinctrl_map_adl = {
.maps = &pinctrl_map_adl[0],
.nmaps = ARRAY_SIZE(pinctrl_map_adl),
};
static const struct dmi_system_id dmi_platform_info[] = {
{
/* UP Squared */
@ -921,6 +934,14 @@ static const struct dmi_system_id dmi_platform_info[] = {
},
.driver_data = (void *)&upboard_pinctrl_map_apl01,
},
{
/* UP Xtreme i12 */
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
DMI_EXACT_MATCH(DMI_BOARD_NAME, "UPX-ADLP01"),
},
.driver_data = (void *)&upboard_pinctrl_map_adl,
},
{ }
};