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drm/msm/dp: Enable support for eDP v1.4+ link rates table

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The MSM DRM driver currently does not support panels which report their
supported link rates via the SUPPORTED_LINK_RATES table.

For panels which do not offer the optional eDP v1.3 fallback via
MAX_LINK_RATE, this will cause a panel probe failure (e.g. Samsung
ATNA30DW01-1 as found in Microsoft Surface Pro 11).

Detect eDP v1.4 panels and parse the SUPPORTED_LINK_RATES table when
present.

Additionally, set the rate using LINK_RATE_SET instead of LINK_BW_SET,
but only if LINK_BW_SET hasn't already been written to.

Signed-off-by: Dale Whinham <daleyo@gmail.com>
Tested-by: Jérôme de Bretagne <jerome.debretagne@gmail.com>
Tested-by: Steev Klimaszewski <threeway@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/695064/
Link: https://lore.kernel.org/r/20251218-drm-msm-edp14-v2-1-2e56c2338ab1@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Dale Whinham 2025-12-18 00:19:32 +00:00 committed by Dmitry Baryshkov
parent 794b0e68ca
commit ed100aa239
3 changed files with 120 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
drivers/gpu/drm/msm/dp/dp_ctrl.c
View File

@ -175,20 +175,28 @@ static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl,
static int msm_dp_aux_link_configure(struct drm_dp_aux *aux,
struct msm_dp_link_info *link)
{
u8 values[2];
u8 lane_count, bw_code;
int err;
values[0] = drm_dp_link_rate_to_bw_code(link->rate);
values[1] = link->num_lanes;
lane_count = link->num_lanes;
if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
err = drm_dp_dpcd_writeb(aux, DP_LANE_COUNT_SET, lane_count);
if (err < 0)
return err;
return 0;
if (link->use_rate_set) {
DRM_DEBUG_DP("using LINK_RATE_SET: 0x%02x", link->rate_set);
err = drm_dp_dpcd_writeb(aux, DP_LINK_RATE_SET, link->rate_set);
} else {
bw_code = drm_dp_link_rate_to_bw_code(link->rate);
DRM_DEBUG_DP("using LINK_BW_SET: 0x%02x", bw_code);
err = drm_dp_dpcd_writeb(aux, DP_LINK_BW_SET, bw_code);
}
return err;
}
/*
@ -1474,26 +1482,32 @@ static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl,
static int msm_dp_ctrl_link_rate_down_shift(struct msm_dp_ctrl_private *ctrl)
{
int ret = 0;
struct msm_dp_link_info *link_params = &ctrl->link->link_params;
switch (ctrl->link->link_params.rate) {
case 810000:
ctrl->link->link_params.rate = 540000;
break;
case 540000:
ctrl->link->link_params.rate = 270000;
break;
case 270000:
ctrl->link->link_params.rate = 162000;
break;
case 162000:
default:
ret = -EINVAL;
break;
if (link_params->rate_set) {
--link_params->rate_set;
link_params->rate = link_params->supported_rates[link_params->rate_set];
} else {
switch (link_params->rate) {
case 810000:
link_params->rate = 540000;
break;
case 540000:
link_params->rate = 270000;
break;
case 270000:
link_params->rate = 162000;
break;
case 162000:
default:
ret = -EINVAL;
break;
}
}
if (!ret) {
drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
ctrl->link->link_params.rate);
link_params->rate);
}
return ret;

3
drivers/gpu/drm/msm/dp/dp_link.h
View File

@ -17,6 +17,9 @@
struct msm_dp_link_info {
unsigned char revision;
unsigned int rate;
unsigned int supported_rates[DP_MAX_SUPPORTED_RATES];
unsigned int rate_set;
bool use_rate_set;
unsigned int num_lanes;
unsigned long capabilities;
};

93
drivers/gpu/drm/msm/dp/dp_panel.c
View File

@ -13,6 +13,8 @@
#include <drm/drm_print.h>
#include <linux/io.h>
#include <linux/types.h>
#include <asm/byteorder.h>
#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4)
@ -107,29 +109,98 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel)
drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n",
link->max_dp_lanes, link->max_dp_link_rate);
link_info->rate = drm_dp_max_link_rate(dpcd);
max_lttpr_lanes = drm_dp_lttpr_max_lane_count(link->lttpr_common_caps);
max_lttpr_rate = drm_dp_lttpr_max_link_rate(link->lttpr_common_caps);
/* eDP sink */
if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {
u8 edp_rev;
rc = drm_dp_dpcd_read_byte(panel->aux, DP_EDP_DPCD_REV, &edp_rev);
if (rc)
return rc;
drm_dbg_dp(panel->drm_dev, "edp_rev=0x%x\n", edp_rev);
/* For eDP v1.4+, parse the SUPPORTED_LINK_RATES table */
if (edp_rev >= DP_EDP_14) {
__le16 rates[DP_MAX_SUPPORTED_RATES];
u8 bw_set;
int i;
rc = drm_dp_dpcd_read_data(panel->aux, DP_SUPPORTED_LINK_RATES,
rates, sizeof(rates));
if (rc)
return rc;
rc = drm_dp_dpcd_read_byte(panel->aux, DP_LINK_BW_SET, &bw_set);
if (rc)
return rc;
/* Find index of max supported link rate that does not exceed dtsi limits */
for (i = 0; i < ARRAY_SIZE(rates); i++) {
/*
* The value from the DPCD multiplied by 200 gives
* the link rate in kHz. Divide by 10 to convert to
* symbol rate, accounting for 8b/10b encoding.
*/
u32 rate = (le16_to_cpu(rates[i]) * 200) / 10;
if (!rate)
break;
drm_dbg_dp(panel->drm_dev,
"SUPPORTED_LINK_RATES[%d]: %d\n", i, rate);
/*
* Limit link rate from link-frequencies of endpoint
* property of dtsi
*/
if (rate > link->max_dp_link_rate)
break;
/* Limit link rate from LTTPR capabilities, if any */
if (max_lttpr_rate && rate > max_lttpr_rate)
break;
link_info->rate = rate;
link_info->supported_rates[i] = rate;
link_info->rate_set = i;
}
/* Only use LINK_RATE_SET if LINK_BW_SET hasn't already been written to */
if (!bw_set && link_info->rate)
link_info->use_rate_set = true;
}
}
/* Fall back on MAX_LINK_RATE/LINK_BW_SET (DP, eDP <= v1.3) */
if (!link_info->rate) {
link_info->rate = drm_dp_max_link_rate(dpcd);
/* Limit link rate from link-frequencies of endpoint property of dtsi */
if (link_info->rate > link->max_dp_link_rate)
link_info->rate = link->max_dp_link_rate;
/* Limit link rate from LTTPR capabilities, if any */
if (max_lttpr_rate && max_lttpr_rate < link_info->rate)
link_info->rate = max_lttpr_rate;
}
link_info->num_lanes = drm_dp_max_lane_count(dpcd);
/* Limit data lanes from data-lanes of endpoint property of dtsi */
if (link_info->num_lanes > link->max_dp_lanes)
link_info->num_lanes = link->max_dp_lanes;
/* Limit link rate from link-frequencies of endpoint property of dtsi */
if (link_info->rate > link->max_dp_link_rate)
link_info->rate = link->max_dp_link_rate;
/* Limit data lanes from LTTPR capabilities, if any */
max_lttpr_lanes = drm_dp_lttpr_max_lane_count(panel->link->lttpr_common_caps);
if (max_lttpr_lanes && max_lttpr_lanes < link_info->num_lanes)
link_info->num_lanes = max_lttpr_lanes;
/* Limit link rate from LTTPR capabilities, if any */
max_lttpr_rate = drm_dp_lttpr_max_link_rate(panel->link->lttpr_common_caps);
if (max_lttpr_rate && max_lttpr_rate < link_info->rate)
link_info->rate = max_lttpr_rate;
drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
drm_dbg_dp(panel->drm_dev, "link_rate_set=%d\n", link_info->rate_set);
drm_dbg_dp(panel->drm_dev, "use_rate_set=%d\n", link_info->use_rate_set);
drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes);
if (drm_dp_enhanced_frame_cap(dpcd))