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drm/i915/pfit: convert moved code to struct intel_display

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The recently relocated ilk/i9xx panel fitter code is still using struct
drm_i915_private. Convert to struct intel_display.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9967c49291c725037c3266832db4d9d8451dfa38.1740564009.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2025-02-26 12:01:10 +02:00
parent a38a005d95
commit ecab9ac6aa
1 changed files with 25 additions and 26 deletions
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51
drivers/gpu/drm/i915/display/intel_pfit.c
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@ -3,7 +3,6 @@
* Copyright © 2024 Intel Corporation
*/
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_utils.h"
#include "intel_de.h"
@ -557,8 +556,8 @@ int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
enum pipe pipe = crtc->pipe;
int width = drm_rect_width(dst);
@ -573,22 +572,22 @@ void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
* Force use of hard-coded filter coefficients as some pre-programmed
* values are broken, e.g. x201.
*/
if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
if (display->platform.ivybridge || display->platform.haswell)
intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE |
PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
else
intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE |
PF_FILTER_MED_3x3);
intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
intel_de_write_fw(display, PF_WIN_POS(pipe),
PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
intel_de_write_fw(display, PF_WIN_SZ(pipe),
PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
}
void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_display *display = to_intel_display(old_crtc_state);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
/*
@ -598,31 +597,31 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->pch_pfit.enabled)
return;
intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
intel_de_write_fw(display, PF_CTL(pipe), 0);
intel_de_write_fw(display, PF_WIN_POS(pipe), 0);
intel_de_write_fw(display, PF_WIN_SZ(pipe), 0);
}
void ilk_pfit_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 ctl, pos, size;
enum pipe pipe;
ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
ctl = intel_de_read(display, PF_CTL(crtc->pipe));
if ((ctl & PF_ENABLE) == 0)
return;
if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
if (display->platform.ivybridge || display->platform.haswell)
pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
else
pipe = crtc->pipe;
crtc_state->pch_pfit.enabled = true;
pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
pos = intel_de_read(display, PF_WIN_POS(crtc->pipe));
size = intel_de_read(display, PF_WIN_SZ(crtc->pipe));
drm_rect_init(&crtc_state->pch_pfit.dst,
REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
@ -635,7 +634,7 @@ void ilk_pfit_get_config(struct intel_crtc_state *crtc_state)
* ivb/hsw (since we don't use the higher upscaling modes which
* differentiates them) so just WARN about this case for now.
*/
drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
drm_WARN_ON(display->drm, pipe != crtc->pipe);
}
void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@ -680,31 +679,31 @@ void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
intel_de_write(display, PFIT_CONTROL(display), 0);
}
static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
static bool i9xx_has_pfit(struct intel_display *display)
{
if (IS_I830(dev_priv))
if (display->platform.i830)
return false;
return DISPLAY_VER(dev_priv) >= 4 ||
IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
return DISPLAY_VER(display) >= 4 ||
display->platform.pineview || display->platform.mobile;
}
void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe;
u32 tmp;
if (!i9xx_has_pfit(dev_priv))
if (!i9xx_has_pfit(display))
return;
tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
tmp = intel_de_read(display, PFIT_CONTROL(display));
if (!(tmp & PFIT_ENABLE))
return;
/* Check whether the pfit is attached to our pipe. */
if (DISPLAY_VER(dev_priv) >= 4)
if (DISPLAY_VER(display) >= 4)
pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
else
pipe = PIPE_B;
@ -714,5 +713,5 @@ void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
crtc_state->gmch_pfit.control = tmp;
crtc_state->gmch_pfit.pgm_ratios =
intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv));
intel_de_read(display, PFIT_PGM_RATIOS(display));
}