mirror of
https://github.com/torvalds/linux.git
synced 2026-07-29 02:31:27 +02:00
Qualcomm Arm64 DeviceTree fixes for v6.11
On X1E the GPU node is disabled by default, to be enabled in the individual devices once the developers install the required firmware. The generic EDP panel driver used on the X1E CRD is replaced with the Samsung ATNA45AF01 driver, in order to ensure backlight is brought back up after being turned off. The pin configuration for PCIe-related pins are corrected across all the X1E targets. The PCIe controllers gain a minimum OPP vote, and PCIe domain numbers are corrected. WiFi calibration variant information is added to the Lenovo Yoga Slim 7x, to pick the right data from the firmware packages. The incorrect Adreno SMMU global interrupt is corrected. For IPQ5332, the IRQ triggers for the USB controller are corrected. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmbMnc4VHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FTmEQANIITSDMgMOy6NIqXiCeejSl0wKz /aJhJK9iot+dYzcXZfswNxKDstYB3MJ0TIQMKw0uGZ7dyQS+InpD/+PAR1CX4dPz yEpdWvvMDbnVp3IkkvtLjdBCS2Ri11j9ybheGuQWml8/lZs+YzzHObybygNAkKbj 3w6CiPU4lNSXw0bLkxxldC7Dl3UYAWPVtp3sye31ybS8WMLED1N0ANYVheCV/8YT lFPVrFHW+nI+2iyvEg5lIHu+eprgk3a7u32XCm9RE68NTRxCsEkLlgc0r9mbhqMk i/bKN96In/W4mt15SzOj+/wK1SGKCIgeZhYnkZe86NqvBfojvSvwfzbZhM8VveAM aiUpJ9gRm/1QBZt3V84OkdX3w4+RZKpKfEmk9yMMEcHmrhv039lF8PJEEBYPbsIA 8WAaPQ3iauSz5tz4fhObHwAqSnBMvxV5/5HouRyHJfOBjh6Ui7zieVc0RtVhudsd 6d8P/UdDFOeK2LnOdgniPUVvWAMVM2XsFELmjUb9jRDpi3pd4t+Owvbozg6W2SaD ChVDyAeGVSBlqHBsYX/OvwuXFx/GLj+zo49noFD2Ci/qoxGIy40au9miSwFzMa4K BV/wl6Hi+urlvv89MPJi/CDptYc75tr8Dui9DbWMaYP4g3b02Zej0OP+oJqyx0ZT BRHaDLySwJnAC/v5 =ymuZ -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbPiGEACgkQYKtH/8kJ Uid/RxAA39/ZFMx6QEzhA0KAv4xEm73UDsPV8ozB+5asDeDuht1UHq4nwRSmFJaE 4gy+zMipHl8kMvnYBZv1S7rNJ1D27wKOkGBTJrIznB/UBLPxkFJZnjAy8kMWuu9l /Z6X1Fqf8hkxTNet+70y8j2LCQbhyxBd77SvpHiLjHdxs+JH7Vtl7OHbk6+XXDzj OxJu6Iy7CbS4mGqx5pYpOnnl0g9WE1gNEabmH1kSa+aW1nU2fjGVr9gCu1h4tb/D vD1xb8laNs2FmP+HpcootlWWgD0wzU0u1WU5qBzen1B/qm0WyEp/xyUTvM4EiSeN qb3obRx8EbASmcXUtUIfPR9Sz774Gx3J740V7J7ZikxvUnr2cImC955hZzP8U60b +qiTmiFoqTXt5eb4H+w0aB28z4h5hizT9uV50u1K1awdZIP72IucPqfNkvu95MIR 0C/GZraDQl6j0XJocaXp4nSLk09Vo6uejXMCYGeHIm1CgEOwBiezrPy9BQ96an+E 9Efh+5NLm+qXicFqBdTkJ2q06Qkqv5i+rTXcVDdm2VQScn9/u/FdEktIV3C/20Hp mpGG1BVoWcGNFeldF/65R7uRDzX0zXJnn3nXWTKM16d2YqhAd55i9cHjqMZOZqrc Rg5DTbjRkwS7c+rBOSxmGOx9PpcUYuUeRKyGGCs6z2/2KYmB4ME= =oFQA -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-fixes-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes Qualcomm Arm64 DeviceTree fixes for v6.11 On X1E the GPU node is disabled by default, to be enabled in the individual devices once the developers install the required firmware. The generic EDP panel driver used on the X1E CRD is replaced with the Samsung ATNA45AF01 driver, in order to ensure backlight is brought back up after being turned off. The pin configuration for PCIe-related pins are corrected across all the X1E targets. The PCIe controllers gain a minimum OPP vote, and PCIe domain numbers are corrected. WiFi calibration variant information is added to the Lenovo Yoga Slim 7x, to pick the right data from the firmware packages. The incorrect Adreno SMMU global interrupt is corrected. For IPQ5332, the IRQ triggers for the USB controller are corrected. * tag 'qcom-arm64-fixes-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (23 commits) arm64: dts: qcom: x1e80100: Fix Adreno SMMU global interrupt arm64: dts: qcom: disable GPU on x1e80100 by default arm64: dts: qcom: x1e80100-crd: Fix backlight arm64: dts: qcom: x1e80100-yoga-slim7x: fix missing PCIe4 gpios arm64: dts: qcom: x1e80100-yoga-slim7x: disable PCIe6a perst pull down arm64: dts: qcom: x1e80100-yoga-slim7x: fix up PCIe6a pinctrl node arm64: dts: qcom: x1e80100-yoga-slim7x: fix PCIe4 PHY supply arm64: dts: qcom: x1e80100-vivobook-s15: fix missing PCIe4 gpios arm64: dts: qcom: x1e80100-vivobook-s15: disable PCIe6a perst pull down arm64: dts: qcom: x1e80100-vivobook-s15: fix up PCIe6a pinctrl node arm64: dts: qcom: x1e80100-vivobook-s15: fix PCIe4 PHY supply arm64: dts: qcom: x1e80100-qcp: fix missing PCIe4 gpios arm64: dts: qcom: x1e80100-qcp: disable PCIe6a perst pull down arm64: dts: qcom: x1e80100-qcp: fix up PCIe6a pinctrl node arm64: dts: qcom: x1e80100-qcp: fix PCIe4 PHY supply arm64: dts: qcom: x1e80100-crd: fix missing PCIe4 gpios arm64: dts: qcom: x1e80100-crd: disable PCIe6a perst pull down arm64: dts: qcom: x1e80100-crd: fix up PCIe6a pinctrl node arm64: dts: qcom: x1e80100: add missing PCIe minimum OPP arm64: dts: qcom: x1e80100: fix PCIe domain numbers ... Link: https://lore.kernel.org/r/20240826152426.1648383-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
ec57571b5d
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@ -320,8 +320,8 @@ usb: usb@8af8800 {
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reg = <0x08af8800 0x400>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>,
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<GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>;
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event",
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"dp_hs_phy_irq",
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"dm_hs_phy_irq";
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@ -278,6 +278,13 @@ regulators-6 {
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vdd-l3-supply = <&vreg_s1f_0p7>;
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vdd-s1-supply = <&vph_pwr>;
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vdd-s2-supply = <&vph_pwr>;
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vreg_l3i_0p8: ldo3 {
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regulator-name = "vreg_l3i_0p8";
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regulator-min-microvolt = <880000>;
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regulator-max-microvolt = <920000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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};
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regulators-7 {
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@ -423,11 +430,17 @@ &mdss_dp3_phy {
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};
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&pcie4 {
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perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie4_default>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pcie4_phy {
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vdda-phy-supply = <&vreg_l3j_0p8>;
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vdda-phy-supply = <&vreg_l3i_0p8>;
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vdda-pll-supply = <&vreg_l3e_1p2>;
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status = "okay";
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@ -517,7 +530,30 @@ nvme_reg_en: nvme-reg-en-state {
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bias-disable;
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};
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pcie6a_default: pcie2a-default-state {
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pcie4_default: pcie4-default-state {
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clkreq-n-pins {
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pins = "gpio147";
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function = "pcie4_clk";
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drive-strength = <2>;
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bias-pull-up;
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};
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perst-n-pins {
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pins = "gpio146";
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function = "gpio";
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drive-strength = <2>;
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bias-disable;
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};
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wake-n-pins {
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pins = "gpio148";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie6a_default: pcie6a-default-state {
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clkreq-n-pins {
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pins = "gpio153";
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function = "pcie6a_clk";
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@ -529,7 +565,7 @@ perst-n-pins {
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pins = "gpio152";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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bias-disable;
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};
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wake-n-pins {
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@ -268,7 +268,6 @@ vreg_edp_3p3: regulator-edp-3p3 {
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pinctrl-0 = <&edp_reg_en>;
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pinctrl-names = "default";
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regulator-always-on;
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regulator-boot-on;
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};
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@ -637,6 +636,14 @@ vreg_l3j_0p8: ldo3 {
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};
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};
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&gpu {
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status = "okay";
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zap-shader {
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firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
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};
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};
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&i2c0 {
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clock-frequency = <400000>;
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@ -724,9 +731,13 @@ &mdss_dp3 {
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aux-bus {
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panel {
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compatible = "edp-panel";
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compatible = "samsung,atna45af01", "samsung,atna33xc20";
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enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
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power-supply = <&vreg_edp_3p3>;
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pinctrl-0 = <&edp_bl_en>;
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pinctrl-names = "default";
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port {
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edp_panel_in: endpoint {
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remote-endpoint = <&mdss_dp3_out>;
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@ -756,11 +767,17 @@ &mdss_dp3_phy {
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};
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&pcie4 {
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perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie4_default>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pcie4_phy {
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vdda-phy-supply = <&vreg_l3j_0p8>;
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vdda-phy-supply = <&vreg_l3i_0p8>;
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vdda-pll-supply = <&vreg_l3e_1p2>;
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status = "okay";
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@ -785,6 +802,16 @@ &pcie6a_phy {
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status = "okay";
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};
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&pmc8380_3_gpios {
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edp_bl_en: edp-bl-en-state {
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pins = "gpio4";
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function = "normal";
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power-source = <1>; /* 1.8V */
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input-disable;
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output-enable;
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};
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};
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&qupv3_0 {
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status = "okay";
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};
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@ -931,7 +958,30 @@ nvme_reg_en: nvme-reg-en-state {
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bias-disable;
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};
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pcie6a_default: pcie2a-default-state {
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pcie4_default: pcie4-default-state {
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clkreq-n-pins {
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pins = "gpio147";
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function = "pcie4_clk";
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drive-strength = <2>;
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bias-pull-up;
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};
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perst-n-pins {
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pins = "gpio146";
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function = "gpio";
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drive-strength = <2>;
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bias-disable;
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};
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wake-n-pins {
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pins = "gpio148";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie6a_default: pcie6a-default-state {
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clkreq-n-pins {
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pins = "gpio153";
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function = "pcie6a_clk";
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@ -943,15 +993,15 @@ perst-n-pins {
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pins = "gpio152";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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bias-disable;
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};
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wake-n-pins {
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pins = "gpio154";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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pins = "gpio154";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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tpad_default: tpad-default-state {
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@ -625,16 +625,31 @@ &mdss_dp3_phy {
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};
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&pcie4 {
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perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie4_default>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pcie4_phy {
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vdda-phy-supply = <&vreg_l3j_0p8>;
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vdda-phy-supply = <&vreg_l3i_0p8>;
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vdda-pll-supply = <&vreg_l3e_1p2>;
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status = "okay";
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};
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&pcie4_port0 {
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wifi@0 {
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compatible = "pci17cb,1107";
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reg = <0x10000 0x0 0x0 0x0 0x0>;
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qcom,ath12k-calibration-variant = "LES790";
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};
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};
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&pcie6a {
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perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
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@ -782,7 +797,30 @@ nvme_reg_en: nvme-reg-en-state {
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bias-disable;
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};
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pcie6a_default: pcie2a-default-state {
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pcie4_default: pcie4-default-state {
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clkreq-n-pins {
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pins = "gpio147";
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function = "pcie4_clk";
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drive-strength = <2>;
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bias-pull-up;
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};
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perst-n-pins {
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pins = "gpio146";
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function = "gpio";
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drive-strength = <2>;
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bias-disable;
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};
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wake-n-pins {
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pins = "gpio148";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie6a_default: pcie6a-default-state {
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clkreq-n-pins {
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pins = "gpio153";
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function = "pcie6a_clk";
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@ -794,15 +832,15 @@ perst-n-pins {
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pins = "gpio152";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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bias-disable;
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};
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wake-n-pins {
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pins = "gpio154";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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pins = "gpio154";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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tpad_default: tpad-default-state {
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|
|
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|
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@ -606,6 +606,14 @@ vreg_l3j_0p8: ldo3 {
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};
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||||
};
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&gpu {
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status = "okay";
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zap-shader {
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firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
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||||
};
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||||
};
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||||
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&lpass_tlmm {
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spkr_01_sd_n_active: spkr-01-sd-n-active-state {
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||||
pins = "gpio12";
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||||
|
|
@ -660,11 +668,17 @@ &mdss_dp3_phy {
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|||
};
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||||
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||||
&pcie4 {
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perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3j_0p8>;
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
|
|
@ -804,7 +818,30 @@ nvme_reg_en: nvme-reg-en-state {
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
pcie6a_default: pcie2a-default-state {
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
|
|
@ -816,15 +853,15 @@ perst-n-pins {
|
|||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
wcd_default: wcd-reset-n-active-state {
|
||||
|
|
|
|||
|
|
@ -2901,7 +2901,7 @@ pcie6a: pci@1bf8000 {
|
|||
|
||||
dma-coherent;
|
||||
|
||||
linux,pci-domain = <7>;
|
||||
linux,pci-domain = <6>;
|
||||
num-lanes = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -2959,6 +2959,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|||
"link_down";
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_6A_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
phys = <&pcie6a_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
|
@ -3022,7 +3023,7 @@ pcie4: pci@1c08000 {
|
|||
|
||||
dma-coherent;
|
||||
|
||||
linux,pci-domain = <5>;
|
||||
linux,pci-domain = <4>;
|
||||
num-lanes = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -3080,11 +3081,22 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|||
"link_down";
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_4_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
phys = <&pcie4_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie4_port0: pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
pcie4_phy: phy@1c0e000 {
|
||||
|
|
@ -3155,9 +3167,10 @@ gpu: gpu@3d00000 {
|
|||
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "gfx-mem";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_microcode_mem>;
|
||||
firmware-name = "qcom/gen70500_zap.mbn";
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table {
|
||||
|
|
@ -3288,7 +3301,7 @@ adreno_smmu: iommu@3da0000 {
|
|||
reg = <0x0 0x03da0000 0x0 0x40000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <1>;
|
||||
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user