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arm64: dts: renesas: rzg3s-smarc: Enable SCIF3

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Enable SCIF3.  It is routed to the SER1_UART interface on the RZ SMARC
Carrier II board.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250120130936.1080069-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea 2025-01-20 15:09:35 +02:00 committed by Geert Uytterhoeven
parent 02760e35b5
commit ec32d57b4b
1 changed files with 12 additions and 0 deletions
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12
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
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@ -12,6 +12,7 @@
/ {
aliases {
i2c0 = &i2c0;
serial1 = &scif3;
serial3 = &scif0;
mmc1 = &sdhi1;
};
@ -162,6 +163,11 @@ scif0_pins: scif0 {
<RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
};
scif3_pins: scif3 {
pinmux = <RZG2L_PORT_PINMUX(17, 2, 7)>, /* RXD */
<RZG2L_PORT_PINMUX(17, 3, 7)>; /* TXD */
};
sdhi1_pins: sd1 {
data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
@ -208,6 +214,12 @@ &scif0 {
status = "okay";
};
&scif3 {
pinctrl-names = "default";
pinctrl-0 = <&scif3_pins>;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;