github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-07-28 01:55:51 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

PCI: dwc: ep: Expose integrated eDMA resources via EPC aux-resource API

Browse Source 
Implement the EPC aux-resource API for DesignWare endpoint controllers
with integrated eDMA.

Currently, only report an interrupt-emulation doorbell register
(PCI_EPC_AUX_DOORBELL_MMIO), including its Linux IRQ and the write data
needed to trigger the interrupt.

If the DMA controller MMIO window is already exposed via a
platform-owned fixed BAR subregion, also provide the BAR number and
offset so EPF drivers can reuse it without reprogramming the BAR.

Signed-off-by: Koichiro Den <den@valinux.co.jp>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260414141514.1341429-4-den@valinux.co.jp
This commit is contained in:
Koichiro Den 2026-04-14 23:15:10 +09:00 committed by Manivannan Sadhasivam
parent bfb9502651
commit ec2075cfc6
1 changed files with 119 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

119
drivers/pci/controller/dwc/pcie-designware-ep.c
View File

@ -9,6 +9,7 @@
#include <linux/align.h>
#include <linux/bitfield.h>
#include <linux/of.h>
#include <linux/overflow.h>
#include <linux/platform_device.h>
#include "pcie-designware.h"
@ -817,6 +818,122 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
return ep->ops->get_features(ep);
}
static const struct pci_epc_bar_rsvd_region *
dw_pcie_ep_find_bar_rsvd_region(struct dw_pcie_ep *ep,
enum pci_epc_bar_rsvd_region_type type,
enum pci_barno *bar,
resource_size_t *bar_offset)
{
const struct pci_epc_features *features;
const struct pci_epc_bar_desc *bar_desc;
const struct pci_epc_bar_rsvd_region *r;
int i, j;
if (!ep->ops->get_features)
return NULL;
features = ep->ops->get_features(ep);
if (!features)
return NULL;
for (i = BAR_0; i <= BAR_5; i++) {
bar_desc = &features->bar[i];
if (!bar_desc->nr_rsvd_regions || !bar_desc->rsvd_regions)
continue;
for (j = 0; j < bar_desc->nr_rsvd_regions; j++) {
r = &bar_desc->rsvd_regions[j];
if (r->type != type)
continue;
if (bar)
*bar = i;
if (bar_offset)
*bar_offset = r->offset;
return r;
}
}
return NULL;
}
static int
dw_pcie_ep_get_aux_resources_count(struct pci_epc *epc, u8 func_no,
u8 vfunc_no)
{
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct dw_edma_chip *edma = &pci->edma;
if (!pci->edma_reg_size)
return 0;
if (edma->db_offset == ~0)
return 0;
return 1;
}
static int
dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
struct pci_epc_aux_resource *resources,
int num_resources)
{
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
const struct pci_epc_bar_rsvd_region *rsvd;
struct dw_edma_chip *edma = &pci->edma;
enum pci_barno dma_ctrl_bar = NO_BAR;
resource_size_t db_offset = edma->db_offset;
resource_size_t dma_ctrl_bar_offset = 0;
resource_size_t dma_reg_size;
int count;
count = dw_pcie_ep_get_aux_resources_count(epc, func_no, vfunc_no);
if (count < 0)
return count;
if (num_resources < count)
return -ENOSPC;
if (!count)
return 0;
dma_reg_size = pci->edma_reg_size;
rsvd = dw_pcie_ep_find_bar_rsvd_region(ep,
PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,
&dma_ctrl_bar,
&dma_ctrl_bar_offset);
if (rsvd && rsvd->size < dma_reg_size)
dma_reg_size = rsvd->size;
/*
* For interrupt-emulation doorbells, report a standalone resource
* instead of bundling it into the DMA controller MMIO resource.
*/
if (range_end_overflows_t(resource_size_t, db_offset,
sizeof(u32), dma_reg_size))
return -EINVAL;
resources[0] = (struct pci_epc_aux_resource) {
.type = PCI_EPC_AUX_DOORBELL_MMIO,
.phys_addr = pci->edma_reg_phys + db_offset,
.size = sizeof(u32),
.bar = dma_ctrl_bar,
.bar_offset = dma_ctrl_bar != NO_BAR ?
dma_ctrl_bar_offset + db_offset : 0,
.u.db_mmio = {
.irq = edma->db_irq,
.data = 0, /* write 0 to assert */
},
};
return 0;
}
static const struct pci_epc_ops epc_ops = {
.write_header = dw_pcie_ep_write_header,
.set_bar = dw_pcie_ep_set_bar,
@ -832,6 +949,8 @@ static const struct pci_epc_ops epc_ops = {
.start = dw_pcie_ep_start,
.stop = dw_pcie_ep_stop,
.get_features = dw_pcie_ep_get_features,
.get_aux_resources_count = dw_pcie_ep_get_aux_resources_count,
.get_aux_resources = dw_pcie_ep_get_aux_resources,
};
/**