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drm/xe/rtp: Whitelist OAMERT MMIO trigger registers

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Whitelist OAMERT registers to enable userspace to execute MMIO triggers on
OAMERT units. Registers are whitelisted for compute and copy class engines.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patch.msgid.link/20251205212613.826224-3-ashutosh.dixit@intel.com
This commit is contained in:
Ashutosh Dixit 2025-12-05 13:26:12 -08:00
parent ab39e2a8f7
commit ec02e49f21
1 changed files with 19 additions and 0 deletions
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19
drivers/gpu/drm/xe/xe_reg_whitelist.c
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@ -9,6 +9,7 @@
#include "regs/xe_gt_regs.h" #include "regs/xe_gt_regs.h"
#include "regs/xe_oa_regs.h" #include "regs/xe_oa_regs.h"
#include "regs/xe_regs.h" #include "regs/xe_regs.h"
#include "xe_device.h"
#include "xe_gt_types.h" #include "xe_gt_types.h"
#include "xe_gt_printk.h" #include "xe_gt_printk.h"
#include "xe_platform_types.h" #include "xe_platform_types.h"
@ -26,6 +27,13 @@ static bool match_not_render(const struct xe_device *xe,
return hwe->class != XE_ENGINE_CLASS_RENDER; return hwe->class != XE_ENGINE_CLASS_RENDER;
} }
static bool match_has_mert(const struct xe_device *xe,
const struct xe_gt *gt,
const struct xe_hw_engine *hwe)
{
return xe_device_has_mert((struct xe_device *)xe);
}
static const struct xe_rtp_entry_sr register_whitelist[] = { static const struct xe_rtp_entry_sr register_whitelist[] = {
{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"), { XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
@ -94,6 +102,9 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
OAM_STATUS(XE_OAM_SCMI_1_BASE_ADJ), \ OAM_STATUS(XE_OAM_SCMI_1_BASE_ADJ), \
OAM_HEAD_POINTER(XE_OAM_SCMI_1_BASE_ADJ)) OAM_HEAD_POINTER(XE_OAM_SCMI_1_BASE_ADJ))
#define WHITELIST_OA_MERT_MMIO_TRG \
WHITELIST_OA_MMIO_TRG(OAMERT_MMIO_TRG, OAMERT_STATUS, OAMERT_HEAD_POINTER)
{ XE_RTP_NAME("oag_mmio_trg_rcs"), { XE_RTP_NAME("oag_mmio_trg_rcs"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
ENGINE_CLASS(RENDER)), ENGINE_CLASS(RENDER)),
@ -114,6 +125,14 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
ENGINE_CLASS(VIDEO_ENHANCE)), ENGINE_CLASS(VIDEO_ENHANCE)),
XE_RTP_ACTIONS(WHITELIST_OAM_MMIO_TRG) XE_RTP_ACTIONS(WHITELIST_OAM_MMIO_TRG)
}, },
{ XE_RTP_NAME("oa_mert_mmio_trg_ccs"),
XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COMPUTE)),
XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG)
},
{ XE_RTP_NAME("oa_mert_mmio_trg_bcs"),
XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COPY)),
XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG)
},
}; };
static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)