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https://github.com/torvalds/linux.git
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PCI/pwrctrl: tc9563: Rely on regmap APIs
Replace the custom tc9563_pwrctrl_i2c_{read,write,bulk_write} functions
with standard regmap APIs. The device uses 24-bit big-endian register
addresses and 32-bit little-endian register values over I2C, which is
directly supported by regmap.
This removes the open-coded I2C transfer handling and lets the regmap
core handle formatting, locking, and multi-register coalescing.
Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260729-pci-pwrctrl-tc956x-regmap-v1-1-20ce61a3ce12@oss.qualcomm.com
This commit is contained in:
Lorenzo Bianconi
Bjorn Helgaas
parent
cee9395acd
commit
ebaa06fc5b
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@ -29,6 +29,7 @@ config PCI_PWRCTRL_TC9563
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select PCI_PWRCTRL
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default m if ARCH_QCOM
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depends on I2C
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select REGMAP_I2C
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help
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Say Y here to enable the PCI Power Control driver of TC9563 PCIe
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switch.
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@ -16,10 +16,10 @@
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#include <linux/pci.h>
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#include <linux/pci-pwrctrl.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/unaligned.h>
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#include "../pci.h"
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@ -70,11 +70,6 @@
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#define TC9563_L0S_L1_DELAY_UNIT_NS 256 /* Each unit represents 256 ns */
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struct tc9563_pwrctrl_reg_setting {
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unsigned int offset;
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unsigned int val;
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};
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enum tc9563_pwrctrl_ports {
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TC9563_USP,
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TC9563_DSP1,
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@ -111,13 +106,14 @@ struct tc9563_pwrctrl {
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struct gpio_desc *reset_gpio;
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struct i2c_adapter *adapter;
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struct i2c_client *client;
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struct regmap *regmap;
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};
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/*
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* downstream port power off sequence, hardcoding the address
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* as we don't know register names for these register offsets.
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*/
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static const struct tc9563_pwrctrl_reg_setting common_pwroff_seq[] = {
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static const struct reg_sequence common_pwroff_seq[] = {
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{0x82900c, 0x1},
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{0x829010, 0x1},
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{0x829018, 0x0},
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@ -140,7 +136,7 @@ static const struct tc9563_pwrctrl_reg_setting common_pwroff_seq[] = {
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{0x829114, 0x1},
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};
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static const struct tc9563_pwrctrl_reg_setting dsp1_pwroff_seq[] = {
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static const struct reg_sequence dsp1_pwroff_seq[] = {
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{TC9563_PORT_ACCESS_ENABLE, 0x2},
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{TC9563_PORT_LANE_ACCESS_ENABLE, 0x3},
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{TC9563_POWER_CONTROL, 0x014f4804},
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@ -148,7 +144,7 @@ static const struct tc9563_pwrctrl_reg_setting dsp1_pwroff_seq[] = {
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{TC9563_PORT_ACCESS_ENABLE, 0x4},
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};
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static const struct tc9563_pwrctrl_reg_setting dsp2_pwroff_seq[] = {
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static const struct reg_sequence dsp2_pwroff_seq[] = {
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{TC9563_PORT_ACCESS_ENABLE, 0x8},
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{TC9563_PORT_LANE_ACCESS_ENABLE, 0x1},
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{TC9563_POWER_CONTROL, 0x014f4804},
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@ -156,85 +152,11 @@ static const struct tc9563_pwrctrl_reg_setting dsp2_pwroff_seq[] = {
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{TC9563_PORT_ACCESS_ENABLE, 0x8},
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};
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/*
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* Since all transfers are initiated by the probe, no locks are necessary,
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* as there are no concurrent calls.
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*/
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static int tc9563_pwrctrl_i2c_write(struct i2c_client *client,
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u32 reg_addr, u32 reg_val)
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{
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struct i2c_msg msg;
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u8 msg_buf[7];
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int ret;
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msg.addr = client->addr;
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msg.len = 7;
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msg.flags = 0;
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/* Big Endian for reg addr */
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put_unaligned_be24(reg_addr, &msg_buf[0]);
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/* Little Endian for reg val */
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put_unaligned_le32(reg_val, &msg_buf[3]);
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msg.buf = msg_buf;
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ret = i2c_transfer(client->adapter, &msg, 1);
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return ret == 1 ? 0 : ret;
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}
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static int tc9563_pwrctrl_i2c_read(struct i2c_client *client,
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u32 reg_addr, u32 *reg_val)
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{
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struct i2c_msg msg[2];
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u8 wr_data[3];
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u32 rd_data;
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int ret;
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msg[0].addr = client->addr;
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msg[0].len = 3;
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msg[0].flags = 0;
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/* Big Endian for reg addr */
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put_unaligned_be24(reg_addr, &wr_data[0]);
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msg[0].buf = wr_data;
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msg[1].addr = client->addr;
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msg[1].len = 4;
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msg[1].flags = I2C_M_RD;
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msg[1].buf = (u8 *)&rd_data;
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ret = i2c_transfer(client->adapter, &msg[0], 2);
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if (ret == 2) {
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*reg_val = get_unaligned_le32(&rd_data);
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return 0;
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}
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/* If only one message successfully completed, return -EIO */
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return ret == 1 ? -EIO : ret;
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}
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static int tc9563_pwrctrl_i2c_bulk_write(struct i2c_client *client,
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const struct tc9563_pwrctrl_reg_setting *seq,
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int len)
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{
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int ret, i;
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for (i = 0; i < len; i++) {
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ret = tc9563_pwrctrl_i2c_write(client, seq[i].offset, seq[i].val);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int tc9563_pwrctrl_disable_port(struct tc9563_pwrctrl *tc9563,
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enum tc9563_pwrctrl_ports port)
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{
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struct tc9563_pwrctrl_cfg *cfg = &tc9563->cfg[port];
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const struct tc9563_pwrctrl_reg_setting *seq;
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const struct reg_sequence *seq;
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int ret, len;
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if (!cfg->disable_port)
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@ -254,12 +176,12 @@ static int tc9563_pwrctrl_disable_port(struct tc9563_pwrctrl *tc9563,
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return 0;
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}
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ret = tc9563_pwrctrl_i2c_bulk_write(tc9563->client, seq, len);
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ret = regmap_multi_reg_write(tc9563->regmap, seq, len);
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if (ret)
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return ret;
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return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, common_pwroff_seq,
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ARRAY_SIZE(common_pwroff_seq));
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return regmap_multi_reg_write(tc9563->regmap, common_pwroff_seq,
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ARRAY_SIZE(common_pwroff_seq));
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}
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static int tc9563_pwrctrl_set_port_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9563,
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@ -275,14 +197,13 @@ static int tc9563_pwrctrl_set_port_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9
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/* convert to units of 256ns */
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units = ns / TC9563_L0S_L1_DELAY_UNIT_NS;
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ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_PORT_SELECT,
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BIT(port));
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ret = regmap_write(tc9563->regmap, TC9563_PORT_SELECT, BIT(port));
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if (ret)
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return ret;
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return tc9563_pwrctrl_i2c_write(tc9563->client,
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is_l1 ? TC9563_PORT_L1_DELAY : TC9563_PORT_L0S_DELAY,
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units);
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return regmap_write(tc9563->regmap,
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is_l1 ? TC9563_PORT_L1_DELAY : TC9563_PORT_L0S_DELAY,
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units);
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}
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static int tc9563_pwrctrl_set_eth_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9563,
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@ -297,8 +218,7 @@ static int tc9563_pwrctrl_set_eth_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc95
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/* convert to units of 256ns */
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units = ns / TC9563_L0S_L1_DELAY_UNIT_NS;
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ret = tc9563_pwrctrl_i2c_read(tc9563->client, TC9563_EMBEDDED_ETH_DELAY,
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&rd_val);
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ret = regmap_read(tc9563->regmap, TC9563_EMBEDDED_ETH_DELAY, &rd_val);
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if (ret)
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return ret;
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@ -309,8 +229,7 @@ static int tc9563_pwrctrl_set_eth_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc95
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rd_val = u32_replace_bits(rd_val, units,
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TC9563_ETH_L0S_DELAY_MASK);
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return tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_EMBEDDED_ETH_DELAY,
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rd_val);
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return regmap_write(tc9563->regmap, TC9563_EMBEDDED_ETH_DELAY, rd_val);
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}
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static int tc9563_pwrctrl_set_tx_amplitude(struct tc9563_pwrctrl *tc9563,
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@ -343,14 +262,14 @@ static int tc9563_pwrctrl_set_tx_amplitude(struct tc9563_pwrctrl *tc9563,
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return -EINVAL;
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}
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struct tc9563_pwrctrl_reg_setting tx_amp_seq[] = {
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struct reg_sequence tx_amp_seq[] = {
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{TC9563_PORT_ACCESS_ENABLE, port_access},
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{TC9563_PORT_LANE_ACCESS_ENABLE, 0x3},
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{TC9563_TX_MARGIN, amp},
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};
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return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, tx_amp_seq,
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ARRAY_SIZE(tx_amp_seq));
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return regmap_multi_reg_write(tc9563->regmap, tx_amp_seq,
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ARRAY_SIZE(tx_amp_seq));
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}
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static int tc9563_pwrctrl_disable_dfe(struct tc9563_pwrctrl *tc9563,
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@ -383,7 +302,7 @@ static int tc9563_pwrctrl_disable_dfe(struct tc9563_pwrctrl *tc9563,
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return -EINVAL;
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}
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struct tc9563_pwrctrl_reg_setting disable_dfe_seq[] = {
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struct reg_sequence disable_dfe_seq[] = {
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{TC9563_PORT_ACCESS_ENABLE, port_access},
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{TC9563_PORT_LANE_ACCESS_ENABLE, lane_access},
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{TC9563_DFE_ENABLE, 0x0},
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@ -397,15 +316,15 @@ static int tc9563_pwrctrl_disable_dfe(struct tc9563_pwrctrl *tc9563,
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{TC9563_PHY_RATE_CHANGE_OVERRIDE, 0x0},
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};
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return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, disable_dfe_seq,
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ARRAY_SIZE(disable_dfe_seq));
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return regmap_multi_reg_write(tc9563->regmap, disable_dfe_seq,
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ARRAY_SIZE(disable_dfe_seq));
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}
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static int tc9563_pwrctrl_set_nfts(struct tc9563_pwrctrl *tc9563,
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enum tc9563_pwrctrl_ports port)
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{
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u8 *nfts = tc9563->cfg[port].nfts;
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struct tc9563_pwrctrl_reg_setting nfts_seq[] = {
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struct reg_sequence nfts_seq[] = {
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{TC9563_NFTS_2_5_GT, nfts[0]},
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{TC9563_NFTS_5_GT, nfts[1]},
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};
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@ -420,13 +339,12 @@ static int tc9563_pwrctrl_set_nfts(struct tc9563_pwrctrl *tc9563,
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return 0;
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}
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ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_PORT_SELECT,
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BIT(port));
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ret = regmap_write(tc9563->regmap, TC9563_PORT_SELECT, BIT(port));
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if (ret)
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return ret;
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return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, nfts_seq,
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ARRAY_SIZE(nfts_seq));
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return regmap_multi_reg_write(tc9563->regmap, nfts_seq,
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ARRAY_SIZE(nfts_seq));
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}
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static int tc9563_pwrctrl_assert_deassert_reset(struct tc9563_pwrctrl *tc9563,
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@ -434,14 +352,14 @@ static int tc9563_pwrctrl_assert_deassert_reset(struct tc9563_pwrctrl *tc9563,
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{
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int ret, val;
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ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_GPIO_CONFIG,
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TC9563_GPIO_MASK);
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ret = regmap_write(tc9563->regmap, TC9563_GPIO_CONFIG,
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TC9563_GPIO_MASK);
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if (ret)
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return ret;
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val = deassert ? TC9563_GPIO_DEASSERT_BITS : 0;
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return tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_RESET_GPIO, val);
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return regmap_write(tc9563->regmap, TC9563_RESET_GPIO, val);
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}
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static int tc9563_pwrctrl_parse_device_dt(struct device_node *node,
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@ -572,6 +490,13 @@ static int tc9563_pwrctrl_power_on(struct pci_pwrctrl *pwrctrl)
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return ret;
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}
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static const struct regmap_config tc9563_regmap_config = {
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.reg_bits = 24,
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.val_bits = 32,
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.reg_format_endian = REGMAP_ENDIAN_BIG,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static int tc9563_pwrctrl_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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@ -602,6 +527,14 @@ static int tc9563_pwrctrl_probe(struct platform_device *pdev)
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return PTR_ERR(tc9563->client);
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}
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tc9563->regmap = devm_regmap_init_i2c(tc9563->client,
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&tc9563_regmap_config);
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if (IS_ERR(tc9563->regmap)) {
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ret = dev_err_probe(dev, PTR_ERR(tc9563->regmap),
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"Failed to allocate register map\n");
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goto remove_i2c;
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}
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for (int i = 0; i < ARRAY_SIZE(tc9563_supply_names); i++)
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tc9563->supplies[i].supply = tc9563_supply_names[i];
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