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perf headers: Sync perf_event.h/perf_regs.h with the kernel headers

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Sync the UAPI header changes of supporting SIMD/eGPRs/SSP sampling into
corresponding tools UAPI headers.

Additionally, support the new introduced perf_event_attr fields in the
perf_event_attr__fprintf and perf_event__attr_swap() helpers, and add
sanity check for the new introduced __reserved_4 field in
perf_attr_check().

Co-developed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Dapeng Mi 2026-09-14 09:40:43 +08:00 committed by Arnaldo Carvalho de Melo
parent 7846bf499d
commit eb89aef367
5 changed files with 117 additions and 6 deletions
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53
tools/arch/x86/include/uapi/asm/perf_regs.h
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@ -2,6 +2,8 @@
#ifndef _ASM_X86_PERF_REGS_H #ifndef _ASM_X86_PERF_REGS_H
#define _ASM_X86_PERF_REGS_H #define _ASM_X86_PERF_REGS_H
#include <linux/bits.h>
enum perf_event_x86_regs { enum perf_event_x86_regs {
PERF_REG_X86_AX, PERF_REG_X86_AX,
PERF_REG_X86_BX, PERF_REG_X86_BX,
@ -27,9 +29,35 @@ enum perf_event_x86_regs {
PERF_REG_X86_R13, PERF_REG_X86_R13,
PERF_REG_X86_R14, PERF_REG_X86_R14,
PERF_REG_X86_R15, PERF_REG_X86_R15,
/*
* The eGPRs/SSP and XMM have overlaps. Only one can be used
* at a time. The ABI PERF_SAMPLE_REGS_ABI_SIMD is used to
* distinguish which one is used. If PERF_SAMPLE_REGS_ABI_SIMD
* is set, then eGPRs/SSP is used, otherwise, XMM is used.
*
* Extended GPRs (eGPRs)
*/
PERF_REG_X86_R16,
PERF_REG_X86_R17,
PERF_REG_X86_R18,
PERF_REG_X86_R19,
PERF_REG_X86_R20,
PERF_REG_X86_R21,
PERF_REG_X86_R22,
PERF_REG_X86_R23,
PERF_REG_X86_R24,
PERF_REG_X86_R25,
PERF_REG_X86_R26,
PERF_REG_X86_R27,
PERF_REG_X86_R28,
PERF_REG_X86_R29,
PERF_REG_X86_R30,
PERF_REG_X86_R31,
PERF_REG_X86_SSP,
/* These are the limits for the GPRs. */ /* These are the limits for the GPRs. */
PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1, PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1, PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
PERF_REG_MISC_MAX = PERF_REG_X86_SSP + 1,
/* These all need two bits set because they are 128bit */ /* These all need two bits set because they are 128bit */
PERF_REG_X86_XMM0 = 32, PERF_REG_X86_XMM0 = 32,
@ -54,5 +82,30 @@ enum perf_event_x86_regs {
}; };
#define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1)) #define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1))
#define PERF_X86_EGPRS_MASK __GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R16)
enum {
PERF_X86_SIMD_XMM_REGS = 16,
PERF_X86_SIMD_YMM_REGS = 16,
PERF_X86_SIMD_ZMM_REGS = 32,
PERF_X86_SIMD_VEC_REGS_MAX = PERF_X86_SIMD_ZMM_REGS,
PERF_X86_SIMD_OPMASK_REGS = 8,
PERF_X86_SIMD_PRED_REGS_MAX = PERF_X86_SIMD_OPMASK_REGS,
};
#define PERF_X86_SIMD_PRED_MASK __GENMASK(PERF_X86_SIMD_PRED_REGS_MAX - 1, 0)
#define PERF_X86_SIMD_VEC_MASK __GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0)
#define PERF_X86_H16ZMM_BASE 16
enum {
/* 1 qword = 8 bytes */
PERF_X86_OPMASK_QWORDS = 1,
PERF_X86_XMM_QWORDS = 2,
PERF_X86_YMM_QWORDS = 4,
PERF_X86_ZMM_QWORDS = 8,
PERF_X86_SIMD_QWORDS_MAX = PERF_X86_ZMM_QWORDS,
};
#endif /* _ASM_X86_PERF_REGS_H */ #endif /* _ASM_X86_PERF_REGS_H */

49
tools/include/uapi/linux/perf_event.h
View File

@ -314,8 +314,9 @@ enum {
*/ */
enum perf_sample_regs_abi { enum perf_sample_regs_abi {
PERF_SAMPLE_REGS_ABI_NONE = 0, PERF_SAMPLE_REGS_ABI_NONE = 0,
PERF_SAMPLE_REGS_ABI_32 = 1, PERF_SAMPLE_REGS_ABI_32 = (1 << 0),
PERF_SAMPLE_REGS_ABI_64 = 2, PERF_SAMPLE_REGS_ABI_64 = (1 << 1),
PERF_SAMPLE_REGS_ABI_SIMD = (1 << 2),
}; };
/* /*
@ -383,6 +384,7 @@ enum perf_event_read_format {
#define PERF_ATTR_SIZE_VER7 128 /* Add: sig_data */ #define PERF_ATTR_SIZE_VER7 128 /* Add: sig_data */
#define PERF_ATTR_SIZE_VER8 136 /* Add: config3 */ #define PERF_ATTR_SIZE_VER8 136 /* Add: config3 */
#define PERF_ATTR_SIZE_VER9 144 /* add: config4 */ #define PERF_ATTR_SIZE_VER9 144 /* add: config4 */
#define PERF_ATTR_SIZE_VER10 176 /* Add: sample_simd_{vec|pred}_reg_* */
/* /*
* 'struct perf_event_attr' contains various attributes that define * 'struct perf_event_attr' contains various attributes that define
@ -547,6 +549,29 @@ struct perf_event_attr {
__u64 config3; /* extension of config2 */ __u64 config3; /* extension of config2 */
__u64 config4; /* extension of config3 */ __u64 config4; /* extension of config3 */
/*
* Defines the sampling SIMD/PRED(predicate) registers bitmap and
* qwords (8 bytes) length.
*
* sample_simd_regs_enabled != 0 indicates there are SIMD/PRED
* registers to be sampled, the SIMD/PRED registers bitmap and
* qwords length are represented in
* sample_simd_{vec|pred}_reg_{intr|user} and
* sample_simd_{vec|pred}_reg_qwords fields separately.
*
* sample_simd_regs_enabled == 0 indicates no SIMD/PRED registers
* are sampled.
*/
__u16 sample_simd_regs_enabled;
__u16 sample_simd_pred_reg_qwords;
__u16 sample_simd_vec_reg_qwords;
__u16 __reserved_4;
__u32 sample_simd_pred_reg_intr;
__u32 sample_simd_pred_reg_user;
__u64 sample_simd_vec_reg_intr;
__u64 sample_simd_vec_reg_user;
}; };
/* /*
@ -1020,7 +1045,15 @@ enum perf_event_type {
* } && PERF_SAMPLE_BRANCH_STACK * } && PERF_SAMPLE_BRANCH_STACK
* *
* { u64 abi; # enum perf_sample_regs_abi * { u64 abi; # enum perf_sample_regs_abi
* u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER * u64 regs[weight(mask)];
* struct {
* u64 nr_vectors; # 0 ... weight(sample_simd_vec_reg_user)
* u64 vector_qwords; # 0 ... sample_simd_vec_reg_qwords
* u64 nr_pred; # 0 ... weight(sample_simd_pred_reg_user)
* u64 pred_qwords; # 0 ... sample_simd_pred_reg_qwords
* u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords];
* } && (abi & PERF_SAMPLE_REGS_ABI_SIMD)
* } && PERF_SAMPLE_REGS_USER
* *
* { u64 size; * { u64 size;
* char data[size]; * char data[size];
@ -1047,7 +1080,15 @@ enum perf_event_type {
* { u64 data_src; } && PERF_SAMPLE_DATA_SRC * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
* { u64 transaction; } && PERF_SAMPLE_TRANSACTION * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
* { u64 abi; # enum perf_sample_regs_abi * { u64 abi; # enum perf_sample_regs_abi
* u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR * u64 regs[weight(mask)];
* struct {
* u64 nr_vectors; # 0 ... weight(sample_simd_vec_reg_intr)
* u64 vector_qwords; # 0 ... sample_simd_vec_reg_qwords
* u64 nr_pred; # 0 ... weight(sample_simd_pred_reg_intr)
* u64 pred_qwords; # 0 ... sample_simd_pred_reg_qwords
* u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords];
* } && (abi & PERF_SAMPLE_REGS_ABI_SIMD)
* } && PERF_SAMPLE_REGS_INTR
* { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR
* { u64 cgroup;} && PERF_SAMPLE_CGROUP * { u64 cgroup;} && PERF_SAMPLE_CGROUP
* { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE

3
tools/perf/util/header.c
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@ -2185,7 +2185,8 @@ static void free_event_desc(struct evsel *events)
static bool perf_attr_check(struct perf_event_attr *attr) static bool perf_attr_check(struct perf_event_attr *attr)
{ {
if (attr->__reserved_1 || attr->__reserved_2 || attr->__reserved_3) { if (attr->__reserved_1 || attr->__reserved_2 ||
attr->__reserved_3 || attr->__reserved_4) {
pr_warning("Reserved bits are set unexpectedly. " pr_warning("Reserved bits are set unexpectedly. "
"Please update perf tool.\n"); "Please update perf tool.\n");
return false; return false;

11
tools/perf/util/perf_event_attr_fprintf.c
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@ -407,8 +407,17 @@ int perf_event_attr__fprintf(FILE *fp, struct perf_event_attr *attr,
} }
if (attr_size >= offsetof(struct perf_event_attr, config4)) if (attr_size >= offsetof(struct perf_event_attr, config4))
PRINT_ATTRf(config3, p_hex); PRINT_ATTRf(config3, p_hex);
if (attr_size > offsetof(struct perf_event_attr, config4)) if (attr_size >= offsetof(struct perf_event_attr, sample_simd_regs_enabled))
PRINT_ATTRf(config4, p_hex); PRINT_ATTRf(config4, p_hex);
if (attr_size > offsetof(struct perf_event_attr, sample_simd_vec_reg_user)) {
PRINT_ATTRf(sample_simd_regs_enabled, p_unsigned);
PRINT_ATTRf(sample_simd_pred_reg_qwords, p_unsigned);
PRINT_ATTRf(sample_simd_pred_reg_intr, p_hex);
PRINT_ATTRf(sample_simd_pred_reg_user, p_hex);
PRINT_ATTRf(sample_simd_vec_reg_qwords, p_unsigned);
PRINT_ATTRf(sample_simd_vec_reg_intr, p_hex);
PRINT_ATTRf(sample_simd_vec_reg_user, p_hex);
}
return ret; return ret;
} }

7
tools/perf/util/session.c
View File

@ -639,6 +639,13 @@ do { \
bswap_field_64(sig_data); bswap_field_64(sig_data);
bswap_field_64(config3); bswap_field_64(config3);
bswap_field_64(config4); bswap_field_64(config4);
bswap_field_16(sample_simd_regs_enabled);
bswap_field_16(sample_simd_pred_reg_qwords);
bswap_field_16(sample_simd_vec_reg_qwords);
bswap_field_32(sample_simd_pred_reg_intr);
bswap_field_32(sample_simd_pred_reg_user);
bswap_field_64(sample_simd_vec_reg_intr);
bswap_field_64(sample_simd_vec_reg_user);
/* /*
* After read_format are bitfields. Check read_format because * After read_format are bitfields. Check read_format because