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pinctrl: rockchip: Add pinctrl support for rk3308b
The main description for rk3308b is as follows: - Old iomux multiplexing extension; - GRF_SOC_CON5 register add some bits; - Newly added GRF_SOC_CON13/15 register. Change-Id: I94bfcae5387aceae14895f1cafa0bfea51bf8b63 Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This commit is contained in:
David Wu
Tao Huang
parent
046dbf0f28
commit
eb743c6a7b
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@ -39,6 +39,7 @@
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/rockchip/cpu.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "core.h"
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@ -342,6 +343,10 @@ struct rockchip_pin_ctrl {
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struct rockchip_mux_route_data *iomux_routes;
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u32 niomux_routes;
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int (*ctrl_data_re_init)(struct rockchip_pin_ctrl *ctrl);
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int (*soc_data_init)(struct rockchip_pinctrl *info);
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void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit);
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@ -723,6 +728,100 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
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},
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};
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static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = {
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{
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.num = 1,
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.pin = 14,
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.reg = 0x28,
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.bit = 12,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 15,
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.reg = 0x2c,
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.bit = 0,
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.mask = 0x3
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}, {
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.num = 1,
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.pin = 18,
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.reg = 0x30,
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.bit = 4,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 19,
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.reg = 0x30,
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.bit = 8,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 20,
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.reg = 0x30,
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.bit = 12,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 21,
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.reg = 0x34,
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.bit = 0,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 22,
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.reg = 0x34,
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.bit = 4,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 23,
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.reg = 0x34,
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.bit = 8,
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.mask = 0xf
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}, {
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.num = 3,
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.pin = 12,
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.reg = 0x68,
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.bit = 8,
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.mask = 0xf
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}, {
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.num = 3,
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.pin = 13,
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.reg = 0x68,
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.bit = 12,
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.mask = 0xf
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}, {
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.num = 2,
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.pin = 2,
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.reg = 0x608,
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.bit = 0,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 3,
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.reg = 0x608,
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.bit = 4,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 16,
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.reg = 0x610,
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.bit = 8,
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.mask = 0x7
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}, {
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.num = 3,
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.pin = 10,
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.reg = 0x610,
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.bit = 0,
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.mask = 0x7
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}, {
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.num = 3,
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.pin = 11,
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.reg = 0x610,
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.bit = 4,
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.mask = 0x7
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},
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};
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static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
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{
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.num = 2,
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@ -1118,12 +1217,198 @@ static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
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/* pdm-clkm-m2 */
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.bank_num = 2,
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.pin = 4,
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.func = 2,
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.func = 3,
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.route_offset = 0x600,
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.route_val = BIT(16 + 2) | BIT(2),
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},
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};
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static struct rockchip_mux_route_data rk3308b_mux_route_data[] = {
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{
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/* rtc_clk */
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.bank_num = 0,
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.pin = 19,
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.func = 1,
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.route_offset = 0x314,
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.route_val = BIT(16 + 0) | BIT(0),
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}, {
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/* uart2_rxm0 */
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.bank_num = 1,
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.pin = 22,
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.func = 2,
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.route_offset = 0x314,
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.route_val = BIT(16 + 2) | BIT(16 + 3),
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}, {
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/* uart2_rxm1 */
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.bank_num = 4,
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.pin = 26,
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.func = 2,
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.route_offset = 0x314,
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.route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
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}, {
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/* i2c3_sdam0 */
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.bank_num = 0,
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.pin = 15,
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.func = 2,
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.route_offset = 0x608,
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.route_val = BIT(16 + 8) | BIT(16 + 9),
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}, {
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/* i2c3_sdam1 */
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.bank_num = 3,
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.pin = 12,
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.func = 2,
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.route_offset = 0x608,
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.route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
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}, {
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/* i2c3_sdam2 */
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.bank_num = 2,
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.pin = 0,
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.func = 3,
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.route_offset = 0x608,
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.route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
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}, {
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/* i2s-8ch-1-sclktxm0 */
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.bank_num = 1,
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.pin = 3,
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.func = 2,
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.route_offset = 0x308,
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.route_val = BIT(16 + 3),
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}, {
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/* i2s-8ch-1-sclkrxm0 */
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.bank_num = 1,
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.pin = 4,
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.func = 2,
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.route_offset = 0x308,
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.route_val = BIT(16 + 3),
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}, {
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/* i2s-8ch-1-sclktxm1 */
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.bank_num = 1,
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.pin = 13,
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.func = 2,
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.route_offset = 0x308,
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.route_val = BIT(16 + 3) | BIT(3),
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}, {
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/* i2s-8ch-1-sclkrxm1 */
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.bank_num = 1,
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.pin = 14,
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.func = 2,
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.route_offset = 0x308,
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.route_val = BIT(16 + 3) | BIT(3),
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}, {
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/* pdm-clkm0 */
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.bank_num = 1,
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.pin = 4,
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.func = 3,
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.route_offset = 0x308,
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.route_val = BIT(16 + 12) | BIT(16 + 13),
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}, {
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/* pdm-clkm1 */
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.bank_num = 1,
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.pin = 14,
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.func = 4,
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.route_offset = 0x308,
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.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
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}, {
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/* pdm-clkm2 */
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.bank_num = 2,
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.pin = 6,
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.func = 2,
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.route_offset = 0x308,
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.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
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}, {
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/* pdm-clkm-m2 */
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.bank_num = 2,
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.pin = 4,
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.func = 3,
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.route_offset = 0x600,
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.route_val = BIT(16 + 2) | BIT(2),
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}, {
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/* spi1_miso */
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.bank_num = 3,
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.pin = 10,
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.func = 3,
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.route_offset = 0x314,
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.route_val = BIT(16 + 9),
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}, {
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/* spi1_miso_m1 */
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.bank_num = 2,
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.pin = 4,
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.func = 2,
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.route_offset = 0x314,
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.route_val = BIT(16 + 9) | BIT(9),
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}, {
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/* owire_m0 */
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.bank_num = 0,
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.pin = 11,
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.func = 3,
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.route_offset = 0x314,
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.route_val = BIT(16 + 10) | BIT(16 + 11),
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}, {
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/* owire_m1 */
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.bank_num = 1,
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.pin = 22,
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.func = 7,
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.route_offset = 0x314,
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.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
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}, {
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/* owire_m2 */
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.bank_num = 2,
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.pin = 2,
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.func = 5,
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.route_offset = 0x314,
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.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
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}, {
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/* can_rxd_m0 */
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.bank_num = 0,
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.pin = 11,
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.func = 2,
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.route_offset = 0x314,
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.route_val = BIT(16 + 12) | BIT(16 + 13),
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}, {
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/* can_rxd_m1 */
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.bank_num = 1,
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.pin = 22,
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.func = 5,
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.route_offset = 0x314,
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.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
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}, {
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/* can_rxd_m2 */
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.bank_num = 2,
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.pin = 2,
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.func = 4,
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.route_offset = 0x314,
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.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
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}, {
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/* mac_rxd0_m0 */
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.bank_num = 1,
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.pin = 20,
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.func = 3,
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.route_offset = 0x314,
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.route_val = BIT(16 + 14),
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}, {
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/* mac_rxd0_m1 */
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.bank_num = 4,
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.pin = 2,
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.func = 2,
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.route_offset = 0x314,
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.route_val = BIT(16 + 14) | BIT(14),
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}, {
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/* uart3_rx */
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.bank_num = 3,
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.pin = 12,
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.func = 4,
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.route_offset = 0x314,
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.route_val = BIT(16 + 15),
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}, {
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/* uart3_rx_m1 */
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.bank_num = 0,
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.pin = 17,
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.func = 3,
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.route_offset = 0x314,
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.route_val = BIT(16 + 15) | BIT(15),
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},
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};
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static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
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{
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/* uart2dbg_rxm0 */
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@ -3407,6 +3692,24 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
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static const struct of_device_id rockchip_pinctrl_dt_match[];
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/* Ctrl data specially handle */
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static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl)
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{
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/*
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* Special for rk3308b, where we need to replace the recalced
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* and routed arrays.
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*/
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if (soc_is_rk3308b()) {
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ctrl->iomux_recalced = rk3308b_mux_recalced_data;
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ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data);
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ctrl->iomux_routes = rk3308b_mux_route_data;
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ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data);
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}
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return 0;
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}
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/* retrieve the soc specific data */
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static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
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struct rockchip_pinctrl *d,
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@ -3439,6 +3742,12 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
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}
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}
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/* Ctrl data re-initialize for some Socs */
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if (ctrl->ctrl_data_re_init) {
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if (ctrl->ctrl_data_re_init(ctrl))
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return NULL;
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}
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grf_offs = ctrl->grf_mux_offset;
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pmu_offs = ctrl->pmu_mux_offset;
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drv_pmu_offs = ctrl->pmu_drv_offset;
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@ -3585,6 +3894,48 @@ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
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static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
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rockchip_pinctrl_resume);
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/* SoC data specially handle */
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/* rk3308b SoC data initialize */
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#define RK3308B_GRF_SOC_CON13 0x608
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#define RK3308B_GRF_SOC_CON15 0x610
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/* RK3308B_GRF_SOC_CON13 */
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#define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10))
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#define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
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#define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
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/* RK3308B_GRF_SOC_CON15 */
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#define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11))
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#define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
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#define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
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static int rk3308b_soc_data_init(struct rockchip_pinctrl *info)
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{
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int ret;
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/*
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* Enable the special ctrl of selected sources.
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*/
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if (soc_is_rk3308b()) {
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ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON13,
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RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL |
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RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL |
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RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL);
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if (ret)
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return ret;
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ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON15,
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RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL |
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RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL |
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RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int rockchip_pinctrl_probe(struct platform_device *pdev)
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{
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struct rockchip_pinctrl *info;
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@ -3656,6 +4007,13 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
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return PTR_ERR(info->regmap_pmu);
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}
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/* Special handle for some Socs */
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if (ctrl->soc_data_init) {
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ret = ctrl->soc_data_init(info);
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if (ret)
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return ret;
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}
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ret = rockchip_gpiolib_register(pdev, info);
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if (ret)
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return ret;
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@ -3929,6 +4287,8 @@ static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
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.niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
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.iomux_routes = rk3308_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
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.ctrl_data_re_init = rk3308b_ctrl_data_re_init,
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.soc_data_init = rk3308b_soc_data_init,
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.pull_calc_reg = rk3308_calc_pull_reg_and_bit,
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.drv_calc_reg = rk3308_calc_drv_reg_and_bit,
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.schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
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