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drm/amdgpu: Add missing offsets in gc_11_0_0_offset.h

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IB1 registers:
regCP_IB1_CMD_BUFSZ
regCP_IB1_BASE_LO
regCP_IB1_BASE_HI
regCP_IB1_BUFSZ
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR

Above registers are part of the asic but not of
the offset file for gc_11_0_0_offset.h and hence
adding them.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sunil Khatri 2024-05-21 19:13:44 +05:30 committed by Alex Deucher
parent 836bc350a5
commit eb14b8f505
1 changed files with 10 additions and 0 deletions
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10
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
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@ -7085,10 +7085,18 @@
#define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX 1
#define regCP_GE_MSINVOC_COUNT_HI 0x20a7
#define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX 1
#define regCP_IB1_CMD_BUFSZ 0x20c0
#define regCP_IB1_CMD_BUFSZ_BASE_IDX 1
#define regCP_IB2_CMD_BUFSZ 0x20c1
#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1
#define regCP_ST_CMD_BUFSZ 0x20c2
#define regCP_ST_CMD_BUFSZ_BASE_IDX 1
#define regCP_IB1_BASE_LO 0x20cc
#define regCP_IB1_BASE_LO_BASE_IDX 1
#define regCP_IB1_BASE_HI 0x20cd
#define regCP_IB1_BASE_HI_BASE_IDX 1
#define regCP_IB1_BUFSZ 0x20ce
#define regCP_IB1_BUFSZ_BASE_IDX 1
#define regCP_IB2_BASE_LO 0x20cf
#define regCP_IB2_BASE_LO_BASE_IDX 1
#define regCP_IB2_BASE_HI 0x20d0
@ -7541,6 +7549,8 @@
#define regCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
#define regCP_MES_DOORBELL_CONTROL6 0x2841
#define regCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
#define regCP_MES_GP0_LO 0x2843
#define regCP_MES_GP0_LO_BASE_IDX 1
#define regCP_MES_GP0_HI 0x2844