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https://github.com/torvalds/linux.git
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soc/tegra: Changes for v7.4-rc1
Adds various bits of core Tegra SoC support for Tegra410, Tegra264 and Tegra210-B01. Tegra234 can now be woken up via PCIe. Some references leak and other fixes round this off. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmrAy+YACgkQ3SOs138+ s6GwyQ/+JshMOuaBn5Wqs7Of+znucA9sX0WCuRQXX6uSpJY0WRaSbBW3WJOERSEo AaftbCRocLOecwdgGROMJEVJ7ZeB6CLsW/51AlbsJN3iquEyLZiuPyikWqe5j8Vm ON+OmO7Il8Ob5xpp43G//Y+Xn7aH1AmcQmQVm1FoZws5xZ87n3HtCJ9sYJfJ3YL/ 2ShJQhjSb+qI5MRh6Siw4aDJib4LiiGWZOLx6SoNQLBzQtav1PPdOr6vUlEou0i1 Itq2wTW0k9puNWErCtuNtyOEqKHsJJ9b4cde0+pVT2TGns+4/aVjNwiBykk0fVDZ d8xicfXcGcILKGhyYVyKFv/4dWTS0qDGCeWTHCBiYv6SUWpP//03aIXjv2trupKG XjxECZ5GBx6itlse/cXKlcNkWLzm1nQS3KdaIIV6BhX+WdFp/21/ltB+wAn94a75 ZkhhVJOhVJ/cVkSFzt530Q7Eszm6HGO3L8H7ntM0iegm2jmJiKYn6BN2SfkmdKdG +oCgAL2DAi2KinKyfUJ4TRkGUsMEQQuSnQIoQJnNbvwK2WjixDRFOfTMh2PyJKdv JVZ80UBk+fX5zBae1Qboq70EiQi70QrJEtPsRK+etIMuHJw14yejPRjAOK0zLE+Z rdQPkM8DHRIjoLAbBSDT9VHCS4is3knpOAodOBEl7GiHddCnuvE= =/QFQ -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmrORmAACgkQmmx57+YA GNlI8BAAl94hkUkXJN34go3LILBV/ZsT4ehWPDkO5kgLHEgE/OwSU3wwZoCbJfHa DYS18FVTKJaCm8uI5Af7tE6dXrlxk+9YF2/mpJLOkAligdVJzmIMLBOGhvic7aBF XgpZXKsw0zWLPFqq7PGjmatp8+8b/vt92OQ4qj7+JxfPwTQNcRDbnTdW32IUrLn7 eFdZRqlFQVEJ3UtLzd9xE27P/G2Cgi9zYttHIsB3cBtvV6Q2hNQJwLd+juYXjXu9 EGGsQQNLNX8h4Qq+dUae7ay0yVvox/3VZ0AiZe4DvwRSrkmyWIWw4lwrLhF6mBA7 KJbTOOwCv8ju9ev3ZggfnL5Mbu5/rvsnMq+uc9j80TbjU0kK79NkiwFnTwHHd0uX kt8v5d+XzcHa5lFodkSC9w4bQ2r0ZFHRrmTgCxcwlrJK/fBY8RNbEY9UfdpobseP 51+WOB179iYZCGcTZyjfzyVWwPrhvPbXs5J0nrsWlwI5fKPKpFacg9ZWSQNhXzSz xPdLoDqMlVZoD5fQ9MIFeCR3dz6lc+ZGuynDz2yXeesfbxQ4tXitjUztKANwN+aJ E23ohEIOlWw5TrA79g/rA0wtLs1zywdUOGd6QPTWzqdmQwayaFh0my7MylmK7wvQ BlUJj8110UakmxJGWpFlRKYNjXRwtcl0VbjnIZjyvPpU0SWmkA4= =kWtj -----END PGP SIGNATURE----- Merge tag 'tegra-for-7.4-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers soc/tegra: Changes for v7.4-rc1 Adds various bits of core Tegra SoC support for Tegra410, Tegra264 and Tegra210-B01. Tegra234 can now be woken up via PCIe. Some references leak and other fixes round this off. * tag 'tegra-for-7.4-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: flowctrl: Release OF node reference on error soc/tegra: pmc: Make sure clk_init_data is fully initialized soc/tegra: fuse: speedo-tegra210: Support revision B01 soc/tegra: fuse: Support revision B01 soc/tegra: pmc: Add Tegra210B01 support soc/tegra: cbb: Fix loggger -> logger typo soc/tegra: pmc: Add PCIe wake event for Tegra234 soc/tegra: fuse: Add Tegra264 support soc/tegra: pmc: Add PMC support for Tegra410 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
eaeb993aa8
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@ -1912,7 +1912,7 @@ static bool print_errlog0(struct seq_file *file, struct tegra194_cbb *cbb)
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/*
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* Print debug information about failed transaction using
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* ErrLog registers of error loggger having ErrVld set
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* ErrLog registers of error logger having ErrVld set
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*/
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static bool print_errloggerX_info(struct seq_file *file, struct tegra194_cbb *cbb,
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int errloggerX)
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@ -195,11 +195,14 @@ static int __init tegra_flowctrl_init(void)
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np = of_find_matching_node(NULL, tegra_flowctrl_match);
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if (np) {
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if (of_address_to_resource(np, 0, &res) < 0) {
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int err = of_address_to_resource(np, 0, &res);
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of_node_put(np);
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if (err < 0) {
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pr_err("failed to get flowctrl register\n");
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return -ENXIO;
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}
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of_node_put(np);
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} else if (IS_ENABLED(CONFIG_ARM)) {
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/*
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* Hardcoded fallback for 32-bit Tegra
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@ -34,6 +34,7 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
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[TEGRA_REVISION_A03] = "A03",
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[TEGRA_REVISION_A03p] = "A03 prime",
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[TEGRA_REVISION_A04] = "A04",
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[TEGRA_REVISION_B01] = "B01",
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};
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static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
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@ -65,6 +66,9 @@ static struct tegra_fuse *fuse = &(struct tegra_fuse) {
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};
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static const struct of_device_id tegra_fuse_match[] = {
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#ifdef CONFIG_ARCH_TEGRA_264_SOC
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{ .compatible = "nvidia,tegra264-efuse", .data = &tegra264_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_234_SOC
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{ .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
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#endif
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@ -175,6 +179,11 @@ static int tegra_fuse_probe(struct platform_device *pdev)
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case TEGRA241:
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fuse->soc = &tegra241_fuse_soc;
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break;
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#endif
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#if defined(CONFIG_ARCH_TEGRA_264_SOC)
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case TEGRA264:
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fuse->soc = &tegra264_fuse_soc;
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break;
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#endif
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default:
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return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip);
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@ -413,7 +422,8 @@ const struct attribute_group tegra_soc_attr_group = {
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
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IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
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IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC)
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IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC) || \
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IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC)
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static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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@ -39,7 +39,8 @@
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defined(CONFIG_ARCH_TEGRA_186_SOC) || \
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defined(CONFIG_ARCH_TEGRA_194_SOC) || \
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defined(CONFIG_ARCH_TEGRA_234_SOC) || \
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defined(CONFIG_ARCH_TEGRA_241_SOC)
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defined(CONFIG_ARCH_TEGRA_241_SOC) || \
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defined(CONFIG_ARCH_TEGRA_264_SOC)
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static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
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{
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if (WARN_ON(!fuse->base))
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@ -802,3 +803,168 @@ const struct tegra_fuse_soc tegra241_fuse_soc = {
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.soc_attr_group = &tegra194_soc_attr_group,
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};
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#endif
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#ifdef CONFIG_ARCH_TEGRA_264_SOC
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static const struct nvmem_keepout tegra264_fuse_keepouts[] = {
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{ .start = 0x0019c, .end = 0x001a0 },
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{ .start = 0x00308, .end = 0x00310 },
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{ .start = 0x0032c, .end = 0x00334 },
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{ .start = 0x00350, .end = 0x00354 },
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{ .start = 0x00494, .end = 0x0049c },
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{ .start = 0x0078c, .end = 0x00790 },
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{ .start = 0x007a0, .end = 0x007a8 },
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{ .start = 0x007dc, .end = 0x007e4 },
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{ .start = 0x008d8, .end = 0x008dc },
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{ .start = 0x0096c, .end = 0x00970 },
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{ .start = 0x00974, .end = 0x0097c },
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{ .start = 0x009f4, .end = 0x009f8 },
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{ .start = 0x00a14, .end = 0x00a20 },
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{ .start = 0x00a44, .end = 0x00a4c },
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{ .start = 0x00a50, .end = 0x00a58 },
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{ .start = 0x00a5c, .end = 0x00a64 },
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{ .start = 0x00a68, .end = 0x00a70 },
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{ .start = 0x00acc, .end = 0x00ad0 },
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{ .start = 0x00b0c, .end = 0x00b18 },
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{ .start = 0x00c80, .end = 0x00c8c },
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{ .start = 0x00dac, .end = 0x00db4 },
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{ .start = 0x00db8, .end = 0x00dbc },
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{ .start = 0x00e0c, .end = 0x00e10 },
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{ .start = 0x00fd0, .end = 0x01f00 },
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{ .start = 0x01f1c, .end = 0x10064 },
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{ .start = 0x10084, .end = 0x100a0 },
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{ .start = 0x100a4, .end = 0x1019c },
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{ .start = 0x101a0, .end = 0x101cc },
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{ .start = 0x101d0, .end = 0x10308 },
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{ .start = 0x10310, .end = 0x1055c },
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{ .start = 0x1057c, .end = 0x106b0 },
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{ .start = 0x106b4, .end = 0x11008 },
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{ .start = 0x1100c, .end = 0x11018 },
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{ .start = 0x11020, .end = 0x110b8 },
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{ .start = 0x110c4, .end = 0x110c8 },
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{ .start = 0x110e8, .end = 0x110ec },
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{ .start = 0x110f0, .end = 0x11124 },
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{ .start = 0x11128, .end = 0x11168 },
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{ .start = 0x1116c, .end = 0x111b8 },
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{ .start = 0x111bc, .end = 0x111e4 },
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{ .start = 0x111e8, .end = 0x111ec },
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{ .start = 0x111f0, .end = 0x1121c },
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{ .start = 0x11250, .end = 0x1133c },
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{ .start = 0x11340, .end = 0x113c8 },
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{ .start = 0x113d0, .end = 0x11420 },
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{ .start = 0x11430, .end = 0x11440 },
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{ .start = 0x11444, .end = 0x11468 },
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{ .start = 0x1146c, .end = 0x114a8 },
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{ .start = 0x114ac, .end = 0x115cc },
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{ .start = 0x115d0, .end = 0x115dc },
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{ .start = 0x115e0, .end = 0x116b4 },
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{ .start = 0x116bc, .end = 0x11740 },
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{ .start = 0x11744, .end = 0x117b8 },
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{ .start = 0x117bc, .end = 0x11810 },
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{ .start = 0x11814, .end = 0x11850 },
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{ .start = 0x11858, .end = 0x118a0 },
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{ .start = 0x118ac, .end = 0x11b48 },
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{ .start = 0x11b50, .end = 0x11b5c },
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{ .start = 0x11b60, .end = 0x11bf8 },
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{ .start = 0x11bfc, .end = 0x11c18 },
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{ .start = 0x11c40, .end = 0x12000 },
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{ .start = 0x12004, .end = 0x12010 },
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{ .start = 0x12014, .end = 0x120fc },
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{ .start = 0x1211c, .end = 0x12120 },
|
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{ .start = 0x12124, .end = 0x12144 },
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{ .start = 0x1214c, .end = 0x12300 },
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{ .start = 0x12308, .end = 0x1236c },
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{ .start = 0x12370, .end = 0x126ac },
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{ .start = 0x126b0, .end = 0x12c60 },
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{ .start = 0x12c64, .end = 0x12d94 },
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{ .start = 0x12da4, .end = 0x13004 },
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{ .start = 0x13008, .end = 0x1300c },
|
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{ .start = 0x13010, .end = 0x13014 },
|
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{ .start = 0x13018, .end = 0x13020 },
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{ .start = 0x13064, .end = 0x13084 },
|
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{ .start = 0x130a0, .end = 0x130a4 },
|
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{ .start = 0x130b8, .end = 0x130c4 },
|
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{ .start = 0x130c8, .end = 0x130e8 },
|
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{ .start = 0x130ec, .end = 0x130f0 },
|
||||
{ .start = 0x130fc, .end = 0x1311c },
|
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{ .start = 0x13120, .end = 0x13128 },
|
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{ .start = 0x13144, .end = 0x1314c },
|
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{ .start = 0x13168, .end = 0x1316c },
|
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{ .start = 0x1319c, .end = 0x131a0 },
|
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{ .start = 0x131ac, .end = 0x131c0 },
|
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{ .start = 0x131cc, .end = 0x131d0 },
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{ .start = 0x131e4, .end = 0x131e8 },
|
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{ .start = 0x131ec, .end = 0x131f0 },
|
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{ .start = 0x1321c, .end = 0x13250 },
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{ .start = 0x132f0, .end = 0x13310 },
|
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{ .start = 0x1332c, .end = 0x13334 },
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{ .start = 0x1333c, .end = 0x13344 },
|
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{ .start = 0x13350, .end = 0x13354 },
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{ .start = 0x1336c, .end = 0x13370 },
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{ .start = 0x133ac, .end = 0x133b0 },
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{ .start = 0x133c8, .end = 0x133d0 },
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{ .start = 0x13420, .end = 0x13430 },
|
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{ .start = 0x13440, .end = 0x13444 },
|
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{ .start = 0x13468, .end = 0x13470 },
|
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{ .start = 0x13494, .end = 0x1349c },
|
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{ .start = 0x134a8, .end = 0x134ac },
|
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{ .start = 0x13544, .end = 0x1354c },
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{ .start = 0x1355c, .end = 0x1357c },
|
||||
{ .start = 0x135cc, .end = 0x135e0 },
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{ .start = 0x135e4, .end = 0x13608 },
|
||||
{ .start = 0x1360c, .end = 0x13620 },
|
||||
{ .start = 0x136ac, .end = 0x136bc },
|
||||
{ .start = 0x136c0, .end = 0x136c8 },
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||||
{ .start = 0x13714, .end = 0x13718 },
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||||
{ .start = 0x13724, .end = 0x13728 },
|
||||
{ .start = 0x1372c, .end = 0x13730 },
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||||
{ .start = 0x13734, .end = 0x1373c },
|
||||
{ .start = 0x13740, .end = 0x13744 },
|
||||
{ .start = 0x13754, .end = 0x13758 },
|
||||
{ .start = 0x13760, .end = 0x13784 },
|
||||
{ .start = 0x1378c, .end = 0x13790 },
|
||||
{ .start = 0x137a0, .end = 0x137a8 },
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||||
{ .start = 0x137b8, .end = 0x137bc },
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||||
{ .start = 0x137dc, .end = 0x137e4 },
|
||||
{ .start = 0x137ec, .end = 0x137f0 },
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||||
{ .start = 0x13800, .end = 0x13818 },
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||||
{ .start = 0x13820, .end = 0x13828 },
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||||
{ .start = 0x13830, .end = 0x13858 },
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{ .start = 0x138a0, .end = 0x138b0 },
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{ .start = 0x138d0, .end = 0x138dc },
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{ .start = 0x1396c, .end = 0x13970 },
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{ .start = 0x13974, .end = 0x1397c },
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{ .start = 0x139f4, .end = 0x139f8 },
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{ .start = 0x13a14, .end = 0x13a20 },
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{ .start = 0x13a44, .end = 0x13a4c },
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{ .start = 0x13a50, .end = 0x13a58 },
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{ .start = 0x13a5c, .end = 0x13a64 },
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{ .start = 0x13a68, .end = 0x13a70 },
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{ .start = 0x13acc, .end = 0x13ad8 },
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{ .start = 0x13b0c, .end = 0x13b18 },
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{ .start = 0x13b48, .end = 0x13b50 },
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{ .start = 0x13b5c, .end = 0x13b60 },
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{ .start = 0x13bf8, .end = 0x13bfc },
|
||||
{ .start = 0x13c18, .end = 0x13c40 },
|
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{ .start = 0x13c60, .end = 0x13c64 },
|
||||
{ .start = 0x13c74, .end = 0x13c8c },
|
||||
{ .start = 0x13d94, .end = 0x13da4 },
|
||||
{ .start = 0x13dac, .end = 0x13db4 },
|
||||
{ .start = 0x13db8, .end = 0x13dbc },
|
||||
{ .start = 0x13df4, .end = 0x13e04 },
|
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{ .start = 0x13e0c, .end = 0x13e10 },
|
||||
};
|
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|
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static const struct tegra_fuse_info tegra264_fuse_info = {
|
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.read = tegra30_fuse_read,
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.size = 0x13eb8,
|
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};
|
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|
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const struct tegra_fuse_soc tegra264_fuse_soc = {
|
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.init = tegra30_fuse_init,
|
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.info = &tegra264_fuse_info,
|
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.keepouts = tegra264_fuse_keepouts,
|
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.num_keepouts = ARRAY_SIZE(tegra264_fuse_keepouts),
|
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.soc_attr_group = &tegra194_soc_attr_group,
|
||||
.clk_suspend_on = false,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
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@ -125,7 +125,8 @@ extern const struct tegra_fuse_soc tegra186_fuse_soc;
|
|||
|
||||
#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
|
||||
IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
|
||||
IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC)
|
||||
IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC) || \
|
||||
IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC)
|
||||
extern const struct attribute_group tegra194_soc_attr_group;
|
||||
#endif
|
||||
|
||||
|
|
@ -141,4 +142,8 @@ extern const struct tegra_fuse_soc tegra234_fuse_soc;
|
|||
extern const struct tegra_fuse_soc tegra241_fuse_soc;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_264_SOC
|
||||
extern const struct tegra_fuse_soc tegra264_fuse_soc;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
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|
|
@ -65,7 +65,25 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
|
|||
sku_info->gpu_speedo_id = 0;
|
||||
*threshold = THRESHOLD_INDEX_0;
|
||||
|
||||
if (sku_info->revision >= TEGRA_REVISION_A02) {
|
||||
if (sku_info->revision >= TEGRA_REVISION_B01) {
|
||||
sku_info->gpu_speedo_id = 1;
|
||||
|
||||
switch (sku) {
|
||||
case 0x00: /* Engineering SKU */
|
||||
case 0x01: /* Engineering SKU */
|
||||
case 0x83:
|
||||
break;
|
||||
|
||||
case 0x87:
|
||||
sku_info->cpu_speedo_id = 3;
|
||||
break;
|
||||
|
||||
default:
|
||||
pr_err("Tegra210B01: unknown SKU %#04x\n", sku);
|
||||
/* Using the default for the error case */
|
||||
break;
|
||||
}
|
||||
} else if (sku_info->revision >= TEGRA_REVISION_A02) {
|
||||
switch (sku) {
|
||||
case 0x00: /* Engineering SKU */
|
||||
case 0x01: /* Engineering SKU */
|
||||
|
|
@ -154,7 +172,7 @@ void __init tegra210_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
speedo_revision = get_speedo_revision();
|
||||
pr_info("Speedo Revision %u\n", speedo_revision);
|
||||
|
||||
if (speedo_revision >= 3) {
|
||||
if (sku_info->revision == TEGRA_REVISION_B01 || speedo_revision >= 3) {
|
||||
sku_info->cpu_speedo_value = cpu_speedo[0];
|
||||
sku_info->gpu_speedo_value = cpu_speedo[2];
|
||||
sku_info->soc_speedo_value = soc_speedo[0];
|
||||
|
|
|
|||
|
|
@ -167,30 +167,41 @@ static const struct of_device_id apbmisc_match[] __initconst = {
|
|||
|
||||
void __init tegra_init_revision(void)
|
||||
{
|
||||
u8 chip_id, minor_rev;
|
||||
u8 chip_id, major_rev, minor_rev;
|
||||
|
||||
chip_id = tegra_get_chip_id();
|
||||
major_rev = tegra_get_major_rev();
|
||||
minor_rev = tegra_get_minor_rev();
|
||||
|
||||
switch (minor_rev) {
|
||||
case 1:
|
||||
tegra_sku_info.revision = TEGRA_REVISION_A01;
|
||||
break;
|
||||
case 2:
|
||||
tegra_sku_info.revision = TEGRA_REVISION_A02;
|
||||
break;
|
||||
case 3:
|
||||
if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
|
||||
tegra_fuse_read_spare(19)))
|
||||
tegra_sku_info.revision = TEGRA_REVISION_A03p;
|
||||
else
|
||||
tegra_sku_info.revision = TEGRA_REVISION_A03;
|
||||
break;
|
||||
case 4:
|
||||
tegra_sku_info.revision = TEGRA_REVISION_A04;
|
||||
break;
|
||||
default:
|
||||
tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;
|
||||
if (major_rev > 1) {
|
||||
switch (minor_rev) {
|
||||
case 1:
|
||||
tegra_sku_info.revision = TEGRA_REVISION_B01;
|
||||
break;
|
||||
default:
|
||||
tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;
|
||||
}
|
||||
} else {
|
||||
switch (minor_rev) {
|
||||
case 1:
|
||||
tegra_sku_info.revision = TEGRA_REVISION_A01;
|
||||
break;
|
||||
case 2:
|
||||
tegra_sku_info.revision = TEGRA_REVISION_A02;
|
||||
break;
|
||||
case 3:
|
||||
if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
|
||||
tegra_fuse_read_spare(19)))
|
||||
tegra_sku_info.revision = TEGRA_REVISION_A03p;
|
||||
else
|
||||
tegra_sku_info.revision = TEGRA_REVISION_A03;
|
||||
break;
|
||||
case 4:
|
||||
tegra_sku_info.revision = TEGRA_REVISION_A04;
|
||||
break;
|
||||
default:
|
||||
tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;
|
||||
}
|
||||
}
|
||||
|
||||
tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
#define pr_fmt(fmt) "tegra-pmc: " fmt
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/arm-smccc.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
|
@ -2694,7 +2695,7 @@ tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
|
|||
const struct pmc_clk_init_data *data,
|
||||
unsigned long offset)
|
||||
{
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
struct pmc_clk *pmc_clk;
|
||||
|
||||
pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
|
||||
|
|
@ -2752,7 +2753,7 @@ tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
|
|||
const char *parent_name, unsigned long offset,
|
||||
u32 shift)
|
||||
{
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
struct pmc_clk_gate *gate;
|
||||
|
||||
gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
|
||||
|
|
@ -2980,6 +2981,18 @@ static void tegra_pmc_reset_suspend_mode(void *data)
|
|||
pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
|
||||
}
|
||||
|
||||
static int tegra_pmc_acpi_probe(struct platform_device *pdev, struct tegra_pmc *pmc)
|
||||
{
|
||||
pmc->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(pmc->base))
|
||||
return PTR_ERR(pmc->base);
|
||||
|
||||
tegra_pmc_reset_sysfs_init(pmc);
|
||||
platform_set_drvdata(pdev, pmc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_pmc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_pmc *pmc;
|
||||
|
|
@ -3004,6 +3017,9 @@ static int tegra_pmc_probe(struct platform_device *pdev)
|
|||
mutex_init(&pmc->powergates_lock);
|
||||
pmc->dev = &pdev->dev;
|
||||
|
||||
if (is_acpi_node(dev_fwnode(&pdev->dev)))
|
||||
return tegra_pmc_acpi_probe(pdev, pmc);
|
||||
|
||||
err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
|
||||
if (err < 0)
|
||||
return dev_err_probe(&pdev->dev, err, "failed to parse DT\n");
|
||||
|
|
@ -3900,6 +3916,67 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
|
|||
.has_single_mmio_aperture = true,
|
||||
};
|
||||
|
||||
static const char * const tegra210b01_powergates[] = {
|
||||
[TEGRA_POWERGATE_CPU] = "crail",
|
||||
[TEGRA_POWERGATE_3D] = "3d",
|
||||
[TEGRA_POWERGATE_VENC] = "venc",
|
||||
[TEGRA_POWERGATE_PCIE] = "pcie",
|
||||
[TEGRA_POWERGATE_MPE] = "mpe",
|
||||
[TEGRA_POWERGATE_CPU1] = "cpu1",
|
||||
[TEGRA_POWERGATE_CPU2] = "cpu2",
|
||||
[TEGRA_POWERGATE_CPU3] = "cpu3",
|
||||
[TEGRA_POWERGATE_CPU0] = "cpu0",
|
||||
[TEGRA_POWERGATE_C0NC] = "c0nc",
|
||||
[TEGRA_POWERGATE_SOR] = "sor",
|
||||
[TEGRA_POWERGATE_DIS] = "dis",
|
||||
[TEGRA_POWERGATE_DISB] = "disb",
|
||||
[TEGRA_POWERGATE_XUSBA] = "xusba",
|
||||
[TEGRA_POWERGATE_XUSBB] = "xusbb",
|
||||
[TEGRA_POWERGATE_XUSBC] = "xusbc",
|
||||
[TEGRA_POWERGATE_VIC] = "vic",
|
||||
[TEGRA_POWERGATE_IRAM] = "iram",
|
||||
[TEGRA_POWERGATE_NVDEC] = "nvdec",
|
||||
[TEGRA_POWERGATE_NVJPG] = "nvjpg",
|
||||
[TEGRA_POWERGATE_AUD] = "aud",
|
||||
[TEGRA_POWERGATE_DFD] = "dfd",
|
||||
};
|
||||
|
||||
static const struct tegra_pmc_soc tegra210b01_pmc_soc = {
|
||||
.supports_core_domain = false,
|
||||
.num_powergates = ARRAY_SIZE(tegra210b01_powergates),
|
||||
.powergates = tegra210b01_powergates,
|
||||
.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
|
||||
.cpu_powergates = tegra210_cpu_powergates,
|
||||
.has_tsense_reset = true,
|
||||
.has_gpu_clamps = true,
|
||||
.needs_mbist_war = false,
|
||||
.has_io_pad_wren = true,
|
||||
.maybe_tz_only = true,
|
||||
.num_io_pads = ARRAY_SIZE(tegra210_io_pads),
|
||||
.io_pads = tegra210_io_pads,
|
||||
.num_io_pad_vctrls = ARRAY_SIZE(tegra210_io_pad_vctrls),
|
||||
.io_pad_vctrls = tegra210_io_pad_vctrls,
|
||||
.num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
|
||||
.pin_descs = tegra210_pin_descs,
|
||||
.regs = &tegra20_pmc_regs,
|
||||
.init = tegra20_pmc_init,
|
||||
.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
|
||||
.powergate_set = tegra114_powergate_set,
|
||||
.irq_set_wake = tegra210_pmc_irq_set_wake,
|
||||
.irq_set_type = tegra210_pmc_irq_set_type,
|
||||
.reset_sources = tegra210_reset_sources,
|
||||
.num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
|
||||
.reset_levels = NULL,
|
||||
.num_reset_levels = 0,
|
||||
.num_wake_events = ARRAY_SIZE(tegra210_wake_events),
|
||||
.wake_events = tegra210_wake_events,
|
||||
.pmc_clks_data = tegra_pmc_clks_data,
|
||||
.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
|
||||
.has_blink_output = true,
|
||||
.has_usb_sleepwalk = true,
|
||||
.has_single_mmio_aperture = true,
|
||||
};
|
||||
|
||||
static const struct tegra_io_pad_soc tegra186_io_pads[] = {
|
||||
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, "csia"),
|
||||
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, "csib"),
|
||||
|
|
@ -4421,6 +4498,7 @@ static const char * const tegra234_reset_sources[] = {
|
|||
};
|
||||
|
||||
static const struct tegra_wake_event tegra234_wake_events[] = {
|
||||
TEGRA_WAKE_GPIO("pcie-wake", 1, 0, TEGRA234_MAIN_GPIO(L, 2)),
|
||||
TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)),
|
||||
TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA234_MAIN_GPIO(G, 4)),
|
||||
TEGRA_WAKE_IRQ("pmu", 24, 209),
|
||||
|
|
@ -4820,6 +4898,81 @@ static const struct tegra_pmc_soc tegra264_pmc_soc = {
|
|||
.max_wake_vectors = 4,
|
||||
};
|
||||
|
||||
static const char * const tegra410_reset_sources[] = {
|
||||
"SYS_RESET_N", /* 0x0 */
|
||||
"CSDC_RTC_XTAL",
|
||||
"VREFRO_POWER_BAD",
|
||||
"FMON_32K",
|
||||
"FMON_OSC",
|
||||
"POD_RTC",
|
||||
"POD_IO",
|
||||
"POD_PLUS_IO_SPLL",
|
||||
"POD_PLUS_IO_VMON", /* 0x8 */
|
||||
"POD_PLUS_SOC",
|
||||
"VMON_PLUS_UV",
|
||||
"VMON_PLUS_OV",
|
||||
"FUSECRC_FAULT",
|
||||
"OSC_FAULT",
|
||||
"BPMP_BOOT_FAULT",
|
||||
"SCPM_BPMP_CORE_CLK",
|
||||
"SCPM_PSC_SE_CLK", /* 0x10 */
|
||||
"VMON_SOC_MIN",
|
||||
"VMON_SOC_MAX",
|
||||
"NVJTAG_SEL_MONITOR",
|
||||
"L0_RST_REQ_N",
|
||||
"NV_THERM_FAULT",
|
||||
"PSC_SW",
|
||||
"POD_C2C_LPI_0",
|
||||
"POD_C2C_LPI_1", /* 0x18 */
|
||||
"BPMP_FMON",
|
||||
"FMON_SPLL_OUT",
|
||||
"L1_RST_REQ_N",
|
||||
"OCP_RECOVERY",
|
||||
"AO_WDT_POR",
|
||||
"BPMP_WDT_POR",
|
||||
"RAS_WDT_POR",
|
||||
"TOP_0_WDT_POR", /* 0x20 */
|
||||
"TOP_1_WDT_POR",
|
||||
"TOP_2_WDT_POR",
|
||||
"PSC_WDT_POR",
|
||||
"OOBHUB_WDT_POR",
|
||||
"MSS_SEQ_WDT_POR",
|
||||
"SW_MAIN",
|
||||
"L0L1_RST_OUT_N",
|
||||
"HSM", /* 0x28 */
|
||||
"CSITE_SW",
|
||||
"AO_WDT_DBG",
|
||||
"BPMP_WDT_DBG",
|
||||
"RAS_WDT_DBG",
|
||||
"TOP_0_WDT_DBG",
|
||||
"TOP_1_WDT_DBG",
|
||||
"TOP_2_WDT_DBG",
|
||||
"PSC_WDT_DBG", /* 0x30 */
|
||||
"TSC_0_WDT_DBG",
|
||||
"TSC_1_WDT_DBG",
|
||||
"OOBHUB_WDT_DBG",
|
||||
"MSS_SEQ_WDT_DBG",
|
||||
"L2_RST_REQ_N",
|
||||
"L2_RST_OUT_N",
|
||||
"SC7"
|
||||
};
|
||||
|
||||
static const struct tegra_pmc_regs tegra410_pmc_regs = {
|
||||
.rst_status = 0x8,
|
||||
.rst_source_shift = 0x2,
|
||||
.rst_source_mask = 0xfc,
|
||||
.rst_level_shift = 0x0,
|
||||
.rst_level_mask = 0x3,
|
||||
};
|
||||
|
||||
static const struct tegra_pmc_soc tegra410_pmc_soc = {
|
||||
.regs = &tegra410_pmc_regs,
|
||||
.reset_sources = tegra410_reset_sources,
|
||||
.num_reset_sources = ARRAY_SIZE(tegra410_reset_sources),
|
||||
.reset_levels = tegra186_reset_levels,
|
||||
.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_pmc_match[] = {
|
||||
{ .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra238-pmc", .data = &tegra238_pmc_soc },
|
||||
|
|
@ -4827,6 +4980,7 @@ static const struct of_device_id tegra_pmc_match[] = {
|
|||
{ .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra210b01-pmc", .data = &tegra210b01_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
|
||||
|
|
@ -4835,6 +4989,12 @@ static const struct of_device_id tegra_pmc_match[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
static const struct acpi_device_id tegra_pmc_acpi_match[] = {
|
||||
{ .id = "NVDA2016", .driver_data = (kernel_ulong_t)&tegra410_pmc_soc },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, tegra_pmc_acpi_match);
|
||||
|
||||
static void tegra_pmc_sync_state(struct device *dev)
|
||||
{
|
||||
struct tegra_pmc *pmc = dev_get_drvdata(dev);
|
||||
|
|
@ -4886,6 +5046,7 @@ static struct platform_driver tegra_pmc_driver = {
|
|||
.name = "tegra-pmc",
|
||||
.suppress_bind_attrs = true,
|
||||
.of_match_table = tegra_pmc_match,
|
||||
.acpi_match_table = tegra_pmc_acpi_match,
|
||||
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
|
||||
.pm = &tegra_pmc_pm_ops,
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ enum tegra_revision {
|
|||
TEGRA_REVISION_A03,
|
||||
TEGRA_REVISION_A03p,
|
||||
TEGRA_REVISION_A04,
|
||||
TEGRA_REVISION_B01,
|
||||
TEGRA_REVISION_MAX,
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user