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pinctrl: renesas: Updates for v6.17

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- Use the new GPIO line value setter callbacks,
   - Validate pins before setting a mux function on RZ/G2L.
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Merge tag 'renesas-pinctrl-for-v6.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v6.17

  - Use the new GPIO line value setter callbacks,
  - Validate pins before setting a mux function on RZ/G2L.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij 2025-07-04 00:22:48 +02:00
commit eaa655c2e5
5 changed files with 47 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/pinctrl/renesas/gpio.c
View File

@ -189,9 +189,11 @@ static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
}
static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
static int gpio_pin_set(struct gpio_chip *gc, unsigned int offset, int value)
{
gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
return 0;
}
static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
@ -232,7 +234,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
gc->direction_input = gpio_pin_direction_input;
gc->get = gpio_pin_get;
gc->direction_output = gpio_pin_direction_output;
gc->set = gpio_pin_set;
gc->set_rv = gpio_pin_set;
gc->to_irq = gpio_pin_to_irq;
gc->label = pfc->info->name;

7
drivers/pinctrl/renesas/pinctrl-rza1.c
View File

@ -830,12 +830,13 @@ static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
return rza1_pin_get(port, gpio);
}
static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
int value)
static int rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct rza1_port *port = gpiochip_get_data(chip);
rza1_pin_set(port, gpio, value);
return 0;
}
static const struct gpio_chip rza1_gpiochip_template = {
@ -845,7 +846,7 @@ static const struct gpio_chip rza1_gpiochip_template = {
.direction_input = rza1_gpio_direction_input,
.direction_output = rza1_gpio_direction_output,
.get = rza1_gpio_get,
.set = rza1_gpio_set,
.set_rv = rza1_gpio_set,
};
/* ----------------------------------------------------------------------------
* pinctrl operations

7
drivers/pinctrl/renesas/pinctrl-rza2.c
View File

@ -172,8 +172,7 @@ static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
}
static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
int value)
static int rza2_chip_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
u8 port = RZA2_PIN_ID_TO_PORT(offset);
@ -188,6 +187,8 @@ static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
new_value &= ~BIT(pin);
writeb(new_value, priv->base + RZA2_PODR(port));
return 0;
}
static int rza2_chip_direction_output(struct gpio_chip *chip,
@ -236,7 +237,7 @@ static struct gpio_chip chip = {
.direction_input = rza2_chip_direction_input,
.direction_output = rza2_chip_direction_output,
.get = rza2_chip_get,
.set = rza2_chip_set,
.set_rv = rza2_chip_set,
};
static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)

53
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View File

@ -493,6 +493,23 @@ static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
}
static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl,
u64 cfg, u32 port, u8 bit)
{
u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
u64 data;
if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
return -EINVAL;
data = pctrl->data->port_pin_configs[port];
if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
return -EINVAL;
return 0;
}
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
u8 pin, u8 off, u8 func)
{
@ -536,6 +553,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned int i, *psel_val;
struct group_desc *group;
const unsigned int *pins;
int ret;
func = pinmux_generic_get_function(pctldev, func_selector);
if (!func)
@ -552,6 +570,10 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin);
if (ret)
return ret;
dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);
@ -806,23 +828,6 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
return ret;
}
static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
u64 cfg, u32 port, u8 bit)
{
u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
u64 data;
if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
return -EINVAL;
data = pctrl->data->port_pin_configs[port];
if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
return -EINVAL;
return 0;
}
static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
u8 bit, u32 mask)
{
@ -1287,7 +1292,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
} else {
bit = RZG2L_PIN_ID_TO_PIN(_pin);
if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
return -EINVAL;
}
@ -1447,7 +1452,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
} else {
bit = RZG2L_PIN_ID_TO_PIN(_pin);
if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
return -EINVAL;
}
@ -1687,7 +1692,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
u8 reg8;
int ret;
ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);
ret = rzg2l_validate_pin(pctrl, *pin_data, port, bit);
if (ret)
return ret;
@ -1758,8 +1763,8 @@ static int rzg2l_gpio_direction_input(struct gpio_chip *chip,
return 0;
}
static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
static int rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
@ -1779,6 +1784,8 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
writeb(reg8 & ~BIT(bit), pctrl->base + P(off));
spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
@ -2788,7 +2795,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
chip->direction_input = rzg2l_gpio_direction_input;
chip->direction_output = rzg2l_gpio_direction_output;
chip->get = rzg2l_gpio_get;
chip->set = rzg2l_gpio_set;
chip->set_rv = rzg2l_gpio_set;
chip->label = name;
chip->parent = pctrl->dev;
chip->owner = THIS_MODULE;

8
drivers/pinctrl/renesas/pinctrl-rzv2m.c
View File

@ -790,14 +790,16 @@ static int rzv2m_gpio_direction_input(struct gpio_chip *chip,
return 0;
}
static void rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
static int rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
u32 port = RZV2M_PIN_ID_TO_PORT(offset);
u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
rzv2m_writel_we(pctrl->base + DO(port), bit, !!value);
return 0;
}
static int rzv2m_gpio_direction_output(struct gpio_chip *chip,
@ -955,7 +957,7 @@ static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl)
chip->direction_input = rzv2m_gpio_direction_input;
chip->direction_output = rzv2m_gpio_direction_output;
chip->get = rzv2m_gpio_get;
chip->set = rzv2m_gpio_set;
chip->set_rv = rzv2m_gpio_set;
chip->label = name;
chip->parent = pctrl->dev;
chip->owner = THIS_MODULE;