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arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588

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In preparation to enable the second HDMI output port found on RK3588
SoC, add the related PHY node.  This requires a GRF, hence add the
dependent node as well.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Cristian Ciocaltea 2024-12-11 01:06:15 +02:00 committed by Heiko Stuebner
parent cd81ee8667
commit ea97212a0f
1 changed files with 21 additions and 0 deletions
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21
arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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@ -67,6 +67,11 @@ u2phy1_otg: otg-port {
};
};
hdptxphy1_grf: syscon@fd5e4000 {
compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
reg = <0x0 0xfd5e4000 0x0 0x100>;
};
spdif_tx5: spdif-tx@fddb8000 {
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
reg = <0x0 0xfddb8000 0x0 0x1000>;
@ -429,6 +434,22 @@ sata-port@0 {
};
};
hdptxphy1: phy@fed70000 {
compatible = "rockchip,rk3588-hdptx-phy";
reg = <0x0 0xfed70000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
clock-names = "ref", "apb";
#phy-cells = <0>;
resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
<&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
<&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
<&cru SRST_HDPTX1_LCPLL>;
reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
"lcpll";
rockchip,grf = <&hdptxphy1_grf>;
status = "disabled";
};
usbdp_phy1: phy@fed90000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed90000 0x0 0x10000>;