wifi: ath12k: Move HAL Cookie Conversion and RBM related APIs to wifi7 directory

Move the hardware specific HAL APIs to hal.c file
inside wifi7 directory. These APIs will be called
through the hal_ops mechanism, which are registered
separately by qcn and wcn

Handling following APIs:
ath12k_wifi7_hal_cc_config
ath12k_wifi7_hal_get_idle_link_rbm

Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.4.1-00199-QCAHKSWPL_SILICONZ-1
Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3

Signed-off-by: Pavankumar Nandeshwar <quic_pnandesh@quicinc.com>
Signed-off-by: Ripan Deuri <quic_rdeuri@quicinc.com>
Reviewed-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com>
Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
Link: https://patch.msgid.link/20251009111045.1763001-15-quic_rdeuri@quicinc.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
This commit is contained in:
Pavankumar Nandeshwar 2025-10-09 16:40:41 +05:30 committed by Jeff Johnson
parent 17540a7c9b
commit ea23813a2e
9 changed files with 100 additions and 75 deletions

View File

@ -922,7 +922,7 @@ static int ath12k_core_start(struct ath12k_base *ab)
goto err_hif_stop;
}
ath12k_dp_cc_config(ab);
ath12k_hal_cc_config(ab);
ret = ath12k_dp_rx_pdev_reo_setup(ab);
if (ret) {

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@ -1192,60 +1192,6 @@ static void ath12k_dp_cleanup(struct ath12k_base *ab)
/* Deinit any SOC level resource */
}
void ath12k_dp_cc_config(struct ath12k_base *ab)
{
u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG;
u32 val = 0;
struct ath12k_hal *hal = &ab->hal;
if (ath12k_ftm_mode)
return;
ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(hal), cmem_base);
val |= u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
u32_encode_bits(ATH12K_CC_PPT_MSB,
HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
u32_encode_bits(ATH12K_CC_SPT_MSB,
HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ALIGN) |
u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ENABLE) |
u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE);
ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(hal), val);
/* Enable HW CC for WBM */
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base);
val = u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
u32_encode_bits(ATH12K_CC_PPT_MSB,
HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
u32_encode_bits(ATH12K_CC_SPT_MSB,
HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ALIGN);
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val);
/* Enable conversion complete indication */
val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2);
val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN) |
u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN) |
u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN);
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val);
/* Enable Cookie conversion for WBM2SW Rings */
val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG);
val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN) |
hal->hal_params->wbm2sw_cc_enable;
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val);
}
static u32 ath12k_dp_cc_cookie_gen(u16 ppt_idx, u16 spt_idx)
{
return (u32)ppt_idx << ATH12K_CC_PPT_SHIFT | spt_idx;
@ -1570,24 +1516,6 @@ static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab)
return 0;
}
static enum hal_rx_buf_return_buf_manager
ath12k_dp_get_idle_link_rbm(struct ath12k_base *ab)
{
switch (ab->device_id) {
case 0:
return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST;
case 1:
return HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST;
case 2:
return HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST;
default:
ath12k_warn(ab, "invalid %d device id, so choose default rbm\n",
ab->device_id);
WARN_ON(1);
return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST;
}
}
static int ath12k_dp_setup(struct ath12k_base *ab)
{
struct ath12k_dp *dp;
@ -1605,7 +1533,8 @@ static int ath12k_dp_setup(struct ath12k_base *ab)
spin_lock_init(&dp->reo_cmd_lock);
dp->reo_cmd_cache_flush_count = 0;
dp->idle_link_rbm = ath12k_dp_get_idle_link_rbm(ab);
dp->idle_link_rbm =
ath12k_hal_get_idle_link_rbm(&ab->hal, ab->device_id);
ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc);
if (ret) {

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@ -505,7 +505,6 @@ ath12k_dp_to_pdev_dp(struct ath12k_dp *dp, u8 pdev_idx)
}
void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif);
void ath12k_dp_cc_config(struct ath12k_base *ab);
void ath12k_dp_partner_cc_init(struct ath12k_base *ab);
int ath12k_dp_pdev_alloc(struct ath12k_base *ab);
void ath12k_dp_pdev_pre_alloc(struct ath12k *ar);

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@ -121,6 +121,17 @@ void ath12k_hal_rx_buf_addr_info_get(struct ath12k_hal *hal,
hal->hal_ops->rx_buf_addr_info_get(binfo, paddr, msdu_cookies, rbm);
}
void ath12k_hal_cc_config(struct ath12k_base *ab)
{
ab->hal.hal_ops->cc_config(ab);
}
enum hal_rx_buf_return_buf_manager
ath12k_hal_get_idle_link_rbm(struct ath12k_hal *hal, u8 device_id)
{
return hal->hal_ops->get_idle_link_rbm(hal, device_id);
}
static int ath12k_hal_alloc_cont_rdp(struct ath12k_hal *hal)
{
size_t size;

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@ -1737,6 +1737,9 @@ struct hal_ops {
void (*rx_buf_addr_info_get)(struct ath12k_buffer_addr *binfo,
dma_addr_t *paddr, u32 *msdu_cookies,
u8 *rbm);
void (*cc_config)(struct ath12k_base *ab);
enum hal_rx_buf_return_buf_manager
(*get_idle_link_rbm)(struct ath12k_hal *hal, u8 device_id);
};
u32 ath12k_wifi7_hal_reo_qdesc_size(u32 ba_window_size, u8 tid);
@ -1817,4 +1820,7 @@ void ath12k_hal_rx_buf_addr_info_get(struct ath12k_hal *hal,
struct ath12k_buffer_addr *binfo,
dma_addr_t *paddr, u32 *msdu_cookies,
u8 *rbm);
void ath12k_hal_cc_config(struct ath12k_base *ab);
enum hal_rx_buf_return_buf_manager
ath12k_hal_get_idle_link_rbm(struct ath12k_hal *hal, u8 device_id);
#endif

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@ -630,3 +630,76 @@ void ath12k_wifi7_hal_write_ml_reoq_lut_addr(struct ath12k_base *ab,
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
HAL_REO1_QDESC_LUT_BASE1(&ab->hal), paddr);
}
void ath12k_wifi7_hal_cc_config(struct ath12k_base *ab)
{
u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG;
u32 val = 0;
struct ath12k_hal *hal = &ab->hal;
if (ath12k_ftm_mode)
return;
ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(hal), cmem_base);
val |= u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
u32_encode_bits(ATH12K_CC_PPT_MSB,
HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
u32_encode_bits(ATH12K_CC_SPT_MSB,
HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ALIGN) |
u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ENABLE) |
u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE);
ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(hal), val);
/* Enable HW CC for WBM */
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base);
val = u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
u32_encode_bits(ATH12K_CC_PPT_MSB,
HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
u32_encode_bits(ATH12K_CC_SPT_MSB,
HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ALIGN);
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val);
/* Enable conversion complete indication */
val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2);
val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN) |
u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN) |
u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN);
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val);
/* Enable Cookie conversion for WBM2SW Rings */
val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG);
val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN) |
hal->hal_params->wbm2sw_cc_enable;
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val);
}
enum hal_rx_buf_return_buf_manager
ath12k_wifi7_hal_get_idle_link_rbm(struct ath12k_hal *hal, u8 device_id)
{
switch (device_id) {
case 0:
return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST;
case 1:
return HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST;
case 2:
return HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST;
default:
ath12k_warn(hal,
"invalid %d device id, so choose default rbm\n",
device_id);
WARN_ON(1);
return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST;
}
}

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@ -23,6 +23,9 @@ int ath12k_wifi7_hal_srng_get_ring_id(struct ath12k_hal *hal,
enum hal_ring_type type,
int ring_num, int mac_id);
u32 ath12k_wifi7_hal_ce_get_desc_size(enum hal_ce_desc type);
void ath12k_wifi7_hal_cc_config(struct ath12k_base *ab);
enum hal_rx_buf_return_buf_manager
ath12k_wifi7_hal_get_idle_link_rbm(struct ath12k_hal *hal, u8 device_id);
void ath12k_wifi7_hal_ce_src_set_desc(struct hal_ce_srng_src_desc *desc,
dma_addr_t paddr,
u32 len, u32 id, u8 byte_swap_data);

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@ -1024,5 +1024,7 @@ const struct hal_ops hal_qcn9274_ops = {
.reo_hw_setup = ath12k_wifi7_hal_reo_hw_setup,
.rx_buf_addr_info_set = ath12k_wifi7_hal_rx_buf_addr_info_set,
.rx_buf_addr_info_get = ath12k_wifi7_hal_rx_buf_addr_info_get,
.cc_config = ath12k_wifi7_hal_cc_config,
.get_idle_link_rbm = ath12k_wifi7_hal_get_idle_link_rbm,
};
EXPORT_SYMBOL(hal_qcn9274_ops);

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@ -839,5 +839,7 @@ const struct hal_ops hal_wcn7850_ops = {
.reo_hw_setup = ath12k_wifi7_hal_reo_hw_setup,
.rx_buf_addr_info_set = ath12k_wifi7_hal_rx_buf_addr_info_set,
.rx_buf_addr_info_get = ath12k_wifi7_hal_rx_buf_addr_info_get,
.cc_config = ath12k_wifi7_hal_cc_config,
.get_idle_link_rbm = ath12k_wifi7_hal_get_idle_link_rbm,
};
EXPORT_SYMBOL(hal_wcn7850_ops);