From 6f7549bdb9868009873745439500a6fe15b8513e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 3 Apr 2025 08:43:37 +0200 Subject: [PATCH 01/16] ARM: dts: at91: usb_a9g20: add SPI EEPROM Schematics and board layout indicate that versions with a dataflash instead of an EEPROM might exist. Let's handle that once we have hardware to test. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20250403064336.4846-2-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/usb_a9g20.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/microchip/usb_a9g20.dts b/arch/arm/boot/dts/microchip/usb_a9g20.dts index a2f748141d4b..16caca3ec00d 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20.dts +++ b/arch/arm/boot/dts/microchip/usb_a9g20.dts @@ -11,3 +11,17 @@ / { model = "Calao USB A9G20"; compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; }; + +&spi0 { + cs-gpios = <&pioC 11 GPIO_ACTIVE_LOW>; + status = "okay"; + /* TODO: Some revisions might have a dataflash here instead of an EEPROM */ + eeprom@0 { + compatible = "st,m95640", "atmel,at25"; + reg = <0>; + spi-max-frequency = <2000000>; + size = <8192>; + pagesize = <32>; + address-width = <16>; + }; +}; From 67ba341e57ab158423818ed33bfa1c40eb0e5e7e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 4 Apr 2025 13:27:43 +0200 Subject: [PATCH 02/16] ARM: dts: at91: usb_a9263: fix GPIO for Dataflash chip select Dataflash did not work on my board. After checking schematics and using the proper GPIO, it works now. Also, make it active low to avoid: flash@0 enforce active low on GPIO handle Fixes: 2432d201468d ("ARM: at91: dt: usb-a9263: add dataflash support") Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20250404112742.67416-2-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/usb_a9263.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/usb_a9263.dts b/arch/arm/boot/dts/microchip/usb_a9263.dts index 60d7936dc562..6af450cb387c 100644 --- a/arch/arm/boot/dts/microchip/usb_a9263.dts +++ b/arch/arm/boot/dts/microchip/usb_a9263.dts @@ -58,7 +58,7 @@ usb1: gadget@fff78000 { }; spi0: spi@fffa4000 { - cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioA 5 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { compatible = "atmel,at45", "atmel,dataflash"; From 2b72d99c63dd39dc073422ca1f53a8f46a5c0331 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 2 Apr 2025 22:48:51 +0200 Subject: [PATCH 03/16] ARM: dts: at91: calao_usb: simplify memory node All devices have 64MB RAM. So, the memory node can be put into the most generic DTSI. Signed-off-by: Wolfram Sang Reviewed-by: Alexandre Belloni Link: https://lore.kernel.org/r/20250402204856.5197-2-wsa+renesas@sang-engineering.com [claudiu.beznea: s/can bet put/can be put/g in commit description] Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/usb_a9260.dts | 4 ---- arch/arm/boot/dts/microchip/usb_a9260_common.dtsi | 4 ++++ arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi | 4 ---- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/microchip/usb_a9260.dts b/arch/arm/boot/dts/microchip/usb_a9260.dts index e7f7b259ccf3..de19904e9e91 100644 --- a/arch/arm/boot/dts/microchip/usb_a9260.dts +++ b/arch/arm/boot/dts/microchip/usb_a9260.dts @@ -16,10 +16,6 @@ chosen { bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; }; - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - ahb { apb { shdwc: poweroff@fffffd10 { diff --git a/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi index 8c3530638c6d..b094c31033b5 100644 --- a/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi @@ -16,6 +16,10 @@ main_xtal { }; }; + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + ahb { apb { dbgu: serial@fffff200 { diff --git a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi index f1946e0996b7..b11ad0b29026 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi +++ b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi @@ -14,10 +14,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - i2c-gpio-0 { rtc@56 { compatible = "microcrystal,rv3029"; From 1477dd96e959c1a54546583fb395f0e4ed97d76a Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 2 Apr 2025 22:48:52 +0200 Subject: [PATCH 04/16] ARM: dts: at91: usb_a9260: use 'stdout-path' Do not use the kernel command line for specifying the default serial console. Signed-off-by: Wolfram Sang Reviewed-by: Alexandre Belloni Link: https://lore.kernel.org/r/20250402204856.5197-3-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/usb_a9260.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/usb_a9260.dts b/arch/arm/boot/dts/microchip/usb_a9260.dts index de19904e9e91..1de2864b4cf6 100644 --- a/arch/arm/boot/dts/microchip/usb_a9260.dts +++ b/arch/arm/boot/dts/microchip/usb_a9260.dts @@ -13,7 +13,8 @@ / { compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9"; chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; + stdout-path = "serial0:115200n8"; }; ahb { From 3984cc0f79f5c03b65f3581f48c04cb5e1445c4b Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 2 Apr 2025 22:48:53 +0200 Subject: [PATCH 05/16] ARM: dts: at91: calao_usb: simplify chosen node All devices use equal parameters in 'chosen'. So, the memory node can be put into the most generic DTSI. Signed-off-by: Wolfram Sang Reviewed-by: Alexandre Belloni Link: https://lore.kernel.org/r/20250402204856.5197-4-wsa+renesas@sang-engineering.com [claudiu.beznea: s/can bet put/can be put/g in commit description] Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/usb_a9260.dts | 5 ----- arch/arm/boot/dts/microchip/usb_a9260_common.dtsi | 5 +++++ arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi | 5 ----- 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/microchip/usb_a9260.dts b/arch/arm/boot/dts/microchip/usb_a9260.dts index 1de2864b4cf6..3b61e7145060 100644 --- a/arch/arm/boot/dts/microchip/usb_a9260.dts +++ b/arch/arm/boot/dts/microchip/usb_a9260.dts @@ -12,11 +12,6 @@ / { model = "Calao USB A9260"; compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9"; - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - ahb { apb { shdwc: poweroff@fffffd10 { diff --git a/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi index b094c31033b5..da32c5fdcc47 100644 --- a/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi @@ -6,6 +6,11 @@ */ / { + chosen { + bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; + stdout-path = "serial0:115200n8"; + }; + clocks { slow_xtal { clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi index b11ad0b29026..6bc307c91d65 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi +++ b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi @@ -9,11 +9,6 @@ #include "usb_a9260_common.dtsi" / { - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - i2c-gpio-0 { rtc@56 { compatible = "microcrystal,rv3029"; From dc658570a2c683219545f5ac133bd2ac21ad0938 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 2 Apr 2025 22:48:54 +0200 Subject: [PATCH 06/16] ARM: dts: at91: usb_a9g20: move wrong RTC node Only the LPW variant has the external RTC. Move it to that board specific DT. As a result, the common include for A9G20 boards can go now. Signed-off-by: Wolfram Sang Reviewed-by: Alexandre Belloni Link: https://lore.kernel.org/r/20250402204856.5197-5-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/usb_a9g20.dts | 3 ++- .../boot/dts/microchip/usb_a9g20_common.dtsi | 18 ------------------ arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts | 10 +++++++++- 3 files changed, 11 insertions(+), 20 deletions(-) delete mode 100644 arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi diff --git a/arch/arm/boot/dts/microchip/usb_a9g20.dts b/arch/arm/boot/dts/microchip/usb_a9g20.dts index 16caca3ec00d..555291cd30b3 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20.dts +++ b/arch/arm/boot/dts/microchip/usb_a9g20.dts @@ -5,7 +5,8 @@ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD */ /dts-v1/; -#include "usb_a9g20_common.dtsi" +#include "at91sam9g20.dtsi" +#include "usb_a9260_common.dtsi" / { model = "Calao USB A9G20"; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi deleted file mode 100644 index 6bc307c91d65..000000000000 --- a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a9g20.dts - Device Tree file for Calao USB A9G20 board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9g20.dtsi" -#include "usb_a9260_common.dtsi" - -/ { - i2c-gpio-0 { - rtc@56 { - compatible = "microcrystal,rv3029"; - reg = <0x56>; - }; - }; -}; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts b/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts index 4d104797176c..2eda00477bc5 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts +++ b/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts @@ -5,7 +5,8 @@ * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD */ /dts-v1/; -#include "usb_a9g20_common.dtsi" +#include "at91sam9g20.dtsi" +#include "usb_a9260_common.dtsi" / { model = "Calao USB A9G20 Low Power"; @@ -27,4 +28,11 @@ mmc@0 { }; }; }; + + i2c-gpio-0 { + rtc@56 { + compatible = "microcrystal,rv3029"; + reg = <0x56>; + }; + }; }; From c72ede1c24be689733bcd2233a3a56f2478429c8 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 2 Apr 2025 23:04:46 +0200 Subject: [PATCH 07/16] ARM: dts: at91: at91sam9263: fix NAND chip selects NAND did not work on my USB-A9263. I discovered that the offending commit converted the PIO bank for chip selects wrongly, so all A9263 boards need to be fixed. Fixes: 1004a2977bdc ("ARM: dts: at91: Switch to the new NAND bindings") Signed-off-by: Wolfram Sang Reviewed-by: Alexandre Belloni Link: https://lore.kernel.org/r/20250402210446.5972-2-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91sam9263ek.dts | 2 +- arch/arm/boot/dts/microchip/tny_a9263.dts | 2 +- arch/arm/boot/dts/microchip/usb_a9263.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91sam9263ek.dts b/arch/arm/boot/dts/microchip/at91sam9263ek.dts index 471ea25296aa..93c5268a0845 100644 --- a/arch/arm/boot/dts/microchip/at91sam9263ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9263ek.dts @@ -152,7 +152,7 @@ nand_controller: nand-controller { nand@3 { reg = <0x3 0x0 0x800000>; rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; nand-bus-width = <8>; nand-ecc-mode = "soft"; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/microchip/tny_a9263.dts b/arch/arm/boot/dts/microchip/tny_a9263.dts index 3dd48b3e06da..fd8244b56e05 100644 --- a/arch/arm/boot/dts/microchip/tny_a9263.dts +++ b/arch/arm/boot/dts/microchip/tny_a9263.dts @@ -64,7 +64,7 @@ nand_controller: nand-controller { nand@3 { reg = <0x3 0x0 0x800000>; rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; nand-bus-width = <8>; nand-ecc-mode = "soft"; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/microchip/usb_a9263.dts b/arch/arm/boot/dts/microchip/usb_a9263.dts index 6af450cb387c..8e1a3fb61087 100644 --- a/arch/arm/boot/dts/microchip/usb_a9263.dts +++ b/arch/arm/boot/dts/microchip/usb_a9263.dts @@ -84,7 +84,7 @@ nand_controller: nand-controller { nand@3 { reg = <0x3 0x0 0x800000>; rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; nand-bus-width = <8>; nand-ecc-mode = "soft"; nand-on-flash-bbt; From 37aa981a332003a97957ec912dbb4fb1da84e611 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Tue, 1 Apr 2025 09:13:18 -0700 Subject: [PATCH 08/16] ARM: dts: microchip: sama7d65: Add gmac interfaces for sama7d65 SoC Add support for GMAC interfaces on SAMA7D65 SoC. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/05b107796b6f3a173d0dd0a5b2107b675cfd994e.1743523114.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index b6710ccd4c36..cd17b838e179 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -169,6 +169,38 @@ dma1: dma-controller@e1614000 { status = "disabled"; }; + gmac0: ethernet@e1618000 { + compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; + reg = <0xe1618000 0x2000>; + interrupts = , + , + , + , + , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; + assigned-clock-rates = <125000000>, <200000000>; + status = "disabled"; + }; + + gmac1: ethernet@e161c000 { + compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; + reg = <0xe161c000 0x2000>; + interrupts = , + , + , + , + , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_PERIPHERAL 47>,<&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; + assigned-clock-rates = <125000000>, <200000000>; + status = "disabled"; + }; + pit64b0: timer@e1800000 { compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; reg = <0xe1800000 0x100>; From b51e4aea3ecfe81053dfbb20411b578fc8c6a7ea Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Tue, 1 Apr 2025 09:13:19 -0700 Subject: [PATCH 09/16] ARM: dts: microchip: sama7d65: Add FLEXCOMs to sama7d65 SoC Add FLEXCOMs to the SAMA7D65 SoC device tree. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/d474fcd850978261ac889950ac1c3a36bc6d3926.1743523114.git.Ryan.Wanner@microchip.com [claudiu.beznea: use vendor specific properties at the end of the node, align DMA entries, add missing spaces] Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 267 ++++++++++++++++++++++ 1 file changed, 267 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index cd17b838e179..3949b02efbd3 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -217,6 +217,199 @@ pit64b1: timer@e1804000 { clock-names = "pclk", "gclk"; }; + flx0: flexcom@e1820000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe1820000 0x200>; + ranges = <0x0 0xe1820000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + uart0: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, + <&dma1 AT91_XDMAC_DT_PERID(5)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,usart-mode = ; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(6)>, + <&dma0 AT91_XDMAC_DT_PERID(5)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + flx1: flexcom@e1824000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe1824000 0x200>; + ranges = <0x0 0xe1824000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + spi1: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + flx2: flexcom@e1828000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe1828000 0x200>; + ranges = <0x0 0xe1828000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + uart2: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, + <&dma1 AT91_XDMAC_DT_PERID(9)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,usart-mode = ; + status = "disabled"; + }; + }; + + flx3: flexcom@e182c000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe182c000 0x200>; + ranges = <0x0 0xe182c000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c3: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + #address-cells = <1>; + #size-cells = <1>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, + <&dma0 AT91_XDMAC_DT_PERID(11)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + }; + + flx4: flexcom@e2018000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2018000 0x200>; + ranges = <0x0 0xe2018000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + uart4: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, + <&dma1 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>, + <&dma0 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + flx5: flexcom@e201c000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe201c000 0x200>; + ranges = <0x0 0xe201c000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c5: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, + <&dma0 AT91_XDMAC_DT_PERID(15)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + flx6: flexcom@e2020000 { compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2020000 0x200>; @@ -238,6 +431,80 @@ uart6: serial@200 { }; }; + flx7: flexcom@e2024000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2024000 0x200>; + ranges = <0x0 0xe2024000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + uart7: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, + <&dma1 AT91_XDMAC_DT_PERID(19)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + }; + + flx8: flexcom@e281c000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe281c000 0x200>; + ranges = <0x0 0xe281c000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c8: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + flx9: flexcom@e2820000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2820000 0x200>; + ranges = <0x0 0xe281c000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c9: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + flx10: flexcom@e2824000 { compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2824000 0x200>; From 7116fb2f15cbc16bc3567468816699fa95e5850e Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Tue, 1 Apr 2025 09:13:20 -0700 Subject: [PATCH 10/16] ARM: dts: microchip: sama7d65: Enable GMAC interface Enable GMAC0 interface for sama7d65_curiosity board. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/fca0c1deb74006cdedbdd71061dec9dabf1e9b9a.1743523114.git.Ryan.Wanner@microchip.com [claudiu.beznea: move gmac0 node to keep the nodes alphanumerically sorted, dropped status property on the PHY node, added missing blank line] Signed-off-by: Claudiu Beznea --- .../dts/microchip/at91-sama7d65_curiosity.dts | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 30fdc4f55a3b..d70835b7d0d5 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -60,6 +60,24 @@ &flx10 { status = "okay"; }; +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac0_default + &pinctrl_gmac0_mdio_default + &pinctrl_gmac0_txck_default + &pinctrl_gmac0_phy_irq>; + phy-mode = "rgmii-id"; + status = "okay"; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioa>; + interrupts = ; + }; +}; + &i2c10 { dmas = <0>, <0>; i2c-analog-filter; @@ -106,6 +124,39 @@ &main_xtal { }; &pioa { + pinctrl_gmac0_default: gmac0-default { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + slew-rate = <0>; + bias-disable; + }; + + pinctrl_gmac0_mdio_default: gmac0-mdio-default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_gmac0_phy_irq: gmac0-phy-irq { + pinmux = ; + bias-disable; + }; + + pinctrl_gmac0_txck_default: gmac0-txck-default { + pinmux = ; + slew-rate = <0>; + bias-pull-up; + }; + pinctrl_i2c10_default: i2c10-default{ pinmux = , ; From e65a13a2909658f9fce765d1127274d526c4d490 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Tue, 1 Apr 2025 09:13:21 -0700 Subject: [PATCH 11/16] ARM: dts: microchip: sama7d65: Add MCP16502 to sama7d65 curiosity Add MCP16502 to the sama7d65_curiosity board to control voltages in the MPU. The device is connected to twi 10 interface Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/60f6b7764227bb42c74404e8ca1388477183b7b5.1743523114.git.Ryan.Wanner@microchip.com [claudiu.beznea: drop regulator-suspend-voltage for ldo2 as it is not needed] Signed-off-by: Claudiu Beznea --- .../dts/microchip/at91-sama7d65_curiosity.dts | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index d70835b7d0d5..548c438bc03d 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -30,6 +30,15 @@ memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V_MAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; &dma0 { @@ -117,6 +126,131 @@ channel@4 { label = "VDDCPU"; }; }; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + lvin-supply = <®_5v>; + pvin1-supply = <®_5v>; + pvin2-supply = <®_5v>; + pvin3-supply = <®_5v>; + pvin4-supply = <®_5v>; + status = "okay"; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1050000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddcpu: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-ramp-delay = <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1050000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-standby { + regulator-suspend-microvolt = <1800000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; }; &main_xtal { From 0bbc54da32f6c9d01b5d3baea93bdb4d49b880fb Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Tue, 1 Apr 2025 09:13:22 -0700 Subject: [PATCH 12/16] ARM: dts: microchip: sama7d65_curiosity: add EEPROM If the MAC address is not fetched and loaded by U-boot then Linux will have to load the address. The EEPROM and nvmem-layout to describe EUI48 MAC address regions. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/96ee6832d9b55acfae8d3560f625798025dfd89c.1743523114.git.Ryan.Wanner@microchip.com [claudiu.beznea: added nvmem properties in gmac0 node before the status one] Signed-off-by: Claudiu Beznea --- .../dts/microchip/at91-sama7d65_curiosity.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 548c438bc03d..8057cf9c919a 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -78,6 +78,8 @@ &pinctrl_gmac0_mdio_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; phy-mode = "rgmii-id"; + nvmem-cells = <&eeprom0_eui48>; + nvmem-cell-names = "mac-address"; status = "okay"; ethernet-phy@7 { @@ -251,6 +253,24 @@ regulator-state-mem { }; }; }; + + eeprom0: eeprom@51 { + compatible = "microchip,24aa025e48"; + reg = <0x51>; + size = <256>; + pagesize = <16>; + vcc-supply = <&vdd_3v3>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom0_eui48: eui48@fa { + reg = <0xfa 0x6>; + }; + }; + }; }; &main_xtal { From f5b56abe58b06c5882d0f00f53bfe5073462f694 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Mon, 14 Apr 2025 14:41:26 -0700 Subject: [PATCH 13/16] ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support Add SRAM, secumod, UDDRC, and DDR3phy to enable support for low power modes. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/354ecd628fdd292d2125570a6b10a93cbecb7706.1744666011.git.Ryan.Wanner@microchip.com [claudiu.beznea: keep nodes sorted by their address] Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 3949b02efbd3..f93978e98ac2 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -47,12 +47,37 @@ slow_xtal: clock-slowxtal { }; }; + ns_sram: sram@100000 { + compatible = "mmio-sram"; + reg = <0x100000 0x20000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + }; + soc { compatible = "simple-bus"; ranges; #address-cells = <1>; #size-cells = <1>; + securam: sram@e0000800 { + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xe0000800 0x4000>; + ranges = <0 0xe0000800 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + #address-cells = <1>; + #size-cells = <1>; + no-memory-wc; + }; + + secumod: security-module@e0004000 { + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + }; + sfrbu: sfr@e0008000 { compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; reg = <0xe0008000 0x20>; @@ -526,6 +551,16 @@ i2c10: i2c@600 { }; }; + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; reg = <0xe8c11000 0x1000>, From 4b3d951f288c2ae4f082f13b22899ed190156a65 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Mon, 14 Apr 2025 14:41:27 -0700 Subject: [PATCH 14/16] ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able to store the RTT time data. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/e8868ef06102241b47883ba10edaed751831be6d.1744666011.git.Ryan.Wanner@microchip.com [claudiu.beznea: keep nodes sorted by their address] Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index f93978e98ac2..d08d773b1cc5 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -132,6 +132,13 @@ shdwc: poweroff@e001d200 { status = "disabled"; }; + rtt: rtc@e001d300 { + compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d300 0x30>; + interrupts = ; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>; @@ -139,6 +146,11 @@ clk32k: clock-controller@e001d500 { #clock-cells = <1>; }; + gpbr: syscon@e001d700 { + compatible = "microchip,sama7d65-gpbr", "syscon"; + reg = <0xe001d700 0x48>; + }; + rtc: rtc@e001d800 { compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; reg = <0xe001d800 0x30>; From e634fd7166105c1444249e57fdd01938911f5244 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Mon, 14 Apr 2025 14:41:28 -0700 Subject: [PATCH 15/16] ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board Add RTT timer with backup register for SAMA7D65_Curiosity board. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/463581224a07bf122c6907d34a0c5c71b1cc73e1.1744666011.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 8057cf9c919a..53a657cf4efb 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -346,6 +346,10 @@ pinctrl_uart6_default: uart6-default { }; }; +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + &sdmmc1 { bus-width = <4>; pinctrl-names = "default"; From 36e9e1ab594519972b0b468aec9b8e9591ddd0ac Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Tue, 29 Apr 2025 09:45:47 +0300 Subject: [PATCH 16/16] ARM: dts: microchip: sama7g54_curiosity: Add fixed-partitions for spi-nor flash Add fixed-partitions for spi-nor flash to match the at91 boot flow and layout of the nand flash. Partitions can be listed from /proc/mtd: [root@sama7g54 ~]$ cat /proc/mtd | grep qspi mtd6: 00040000 00001000 "qspi1: at91bootstrap" mtd7: 00100000 00001000 "qspi1: u-boot" mtd8: 00040000 00001000 "qspi1: u-boot env" mtd9: 00080000 00001000 "qspi1: device tree" mtd10: 00600000 00001000 "qspi1: kernel" [root@sama7g54 ~]$ mtdinfo /dev/mtd10 mtd10 Name: qspi1: kernel Type: nor Eraseblock size: 4096 bytes, 4.0 KiB Amount of eraseblocks: 1536 (6291456 bytes, 6.0 MiB) Minimum input/output unit size: 1 byte Sub-page size: 1 byte Character device major/minor: 90:20 Bad blocks are allowed: false Device is writable: true Signed-off-by: Mihai Sain Link: https://lore.kernel.org/r/20250429064547.5807-1-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea --- .../dts/microchip/at91-sama7g54_curiosity.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts index 2dec2218f32c..eb5f27ce1942 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts @@ -369,6 +369,38 @@ flash@0 { spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; + label = "at91-qspi"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "qspi1: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "qspi1: u-boot"; + reg = <0x40000 0x100000>; + }; + + bootloaderenv@140000 { + label = "qspi1: u-boot env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "qspi1: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "qspi1: kernel"; + reg = <0x200000 0x600000>; + }; + }; }; };