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SDMMC:

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1。adjust the IO voltage of ap0 and vccio
2. add the drive strength control
3.Temporary realize even divide of sdmmc-frq.
This commit is contained in:
xbw 2013-01-27 19:36:08 +08:00
parent 570ce374be
commit ea053c81da
2 changed files with 25 additions and 11 deletions
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34
arch/arm/plat-rk/rk-sdmmc-ops.c
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@ -21,20 +21,23 @@
#define SDMMC_USE_NEW_IOMUX_API 0
#endif
//Currently, for the time being does not use this setting.Later, there is a need, then start to use.
//Noted by Michael Xie,at 2013-01-25
#if 0//defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
//GRF_IO_CON2 0x0FC
#define SDMMC0_DRIVER_STRENGTH_2MA (0x00 << 6)
#define SDMMC0_DRIVER_STRENGTH_4MA (0x00 << 6)
#define SDMMC0_DRIVER_STRENGTH_8MA (0x00 << 6)
#define SDMMC0_DRIVER_STRENGTH_12MA (0x00 << 6)
#define SDMMC0_DRIVER_STRENGTH_4MA (0x01 << 6)
#define SDMMC0_DRIVER_STRENGTH_8MA (0x02 << 6)
#define SDMMC0_DRIVER_STRENGTH_12MA (0x03 << 6)
#define SDMMC0_DRIVER_STRENGTH_MASK (0x03 << 22)
//GRF_IO_CON3 0x100
#define SDMMC1_DRIVER_STRENGTH_2MA (0x00 << 2)
#define SDMMC1_DRIVER_STRENGTH_4MA (0x01 << 2)
#define SDMMC1_DRIVER_STRENGTH_8MA (0x10 << 2)
#define SDMMC1_DRIVER_STRENGTH_12MA (0x11 << 2)
#define SDMMC1_DRIVER_STRENGTH_8MA (0x02 << 2)
#define SDMMC1_DRIVER_STRENGTH_12MA (0x03 << 2)
#define SDMMC1_DRIVER_STRENGTH_MASK (0x03 << 18)
#define SDMMC_write_grf_reg(addr, val) __raw_writel(val, addr+RK30_GRF_BASE)
#define SDMMC_read_grf_reg(addr) __raw_readl(addr+RK30_GRF_BASE)
@ -773,8 +776,11 @@ static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
rk30_mux_api_set(rksdmmc0_gpio_init.data0_gpio.iomux.name, rksdmmc0_gpio_init.data0_gpio.iomux.fmux);
#endif
//IO voltage(vccio);sdcard must set the voltage to 3.3v
writel_relaxed(0x10000000, RK30_GRF_BASE + GRF_IO_CON4);
//sdmmc drive strength control
SDMMC_write_grf_reg(GRF_IO_CON2, (SDMMC0_DRIVER_STRENGTH_12MA));
SDMMC_write_grf_reg(GRF_IO_CON2, (SDMMC0_DRIVER_STRENGTH_MASK |SDMMC0_DRIVER_STRENGTH_12MA));
#if !(!!SDMMC_USE_NEW_IOMUX_API)
rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
@ -816,8 +822,16 @@ static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
rk30_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fmux);
#endif
//IO voltage(vcc-ap0)
#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
writel_relaxed(0x01000100, RK30_GRF_BASE + GRF_IO_CON4);
#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)|| defined(CONFIG_MT6620)
writel_relaxed(0x01000000, RK30_GRF_BASE + GRF_IO_CON4);
#endif
//sdmmc1 drive strength control
SDMMC_write_grf_reg(GRF_IO_CON3, (SDMMC1_DRIVER_STRENGTH_12MA));
SDMMC_write_grf_reg(GRF_IO_CON3, (SDMMC1_DRIVER_STRENGTH_MASK|SDMMC1_DRIVER_STRENGTH_12MA));
}

2
include/linux/mmc/mmc.h
View File

@ -349,7 +349,7 @@ struct _mmc_csd {
//In rk2926 machine,very prone to occur data-timeout-error,the machine reduces the frequency.
#define SDHC_FPP_FREQ (39500000) // SDHC in the highspeed. unit is hz, max is 50Mhz.
#else
#define SDHC_FPP_FREQ (49500000) // SDHC in the highspeed. unit is hz, max is 50Mhz.
#define SDHC_FPP_FREQ (43500000) // SDHC in the highspeed. unit is hz, max is 50Mhz.
#endif
#define MMC_FPP_FREQ (19000000) // MMC freq, unit is hz, max is 20MHz
#define MMCHS_26_FPP_FREQ (24000000) // highspeed mode support 26M HS-MMC, unit is hz, max is 26Mhz,