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Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue

Browse Source 
Tony Nguyen says:

====================
libie: commonize adminq structure

Michal Swiatkowski says:

It is a prework to allow reusing some specific Intel code (eq. fwlog).

Move common *_aq_desc structure to libie header and changing
it in ice, ixgbe, i40e and iavf.

Only generic adminq commands can be easily moved to common header, as
rest is slightly different. Format remains the same. It will be better
to correctly move it when it will be needed to commonize other part of
the code.

Move *_aq_str() to new libie module (libie_adminq) and use it across
drivers. The functions are exactly the same in each driver. Some more
adminq helpers/functions can be moved to libie_adminq when needed.

* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
  i40e: use libie_aq_str
  iavf: use libie_aq_str
  ice: use libie_aq_str
  libie: add adminq helper for converting err to str
  iavf: use libie adminq descriptors
  i40e: use libie adminq descriptors
  ixgbe: use libie adminq descriptors
  ice, libie: move generic adminq descriptors to lib
====================

Link: https://patch.msgid.link/20250724182826.3758850-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2025-07-25 16:01:18 -07:00
commit e9e91870ac
59 changed files with 1575 additions and 2142 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/net/ethernet/intel/Kconfig
View File

@ -231,6 +231,7 @@ config I40E
depends on PCI
select AUXILIARY_BUS
select LIBIE
select LIBIE_ADMINQ
select NET_DEVLINK
help
This driver supports Intel(R) Ethernet Controller XL710 Family of
@ -260,6 +261,7 @@ config I40E_DCB
config IAVF
tristate
select LIBIE
select LIBIE_ADMINQ
select NET_SHAPER
config I40EVF
@ -294,6 +296,7 @@ config ICE
select AUXILIARY_BUS
select DIMLIB
select LIBIE
select LIBIE_ADMINQ
select NET_DEVLINK
select PACKING
select PLDMFW

68
drivers/net/ethernet/intel/i40e/i40e_adminq.c
View File

@ -18,7 +18,7 @@ static int i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
(hw->aq.num_asq_entries *
sizeof(struct i40e_aq_desc)),
sizeof(struct libie_aq_desc)),
I40E_ADMINQ_DESC_ALIGNMENT);
if (ret_code)
return ret_code;
@ -44,7 +44,7 @@ static int i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
(hw->aq.num_arq_entries *
sizeof(struct i40e_aq_desc)),
sizeof(struct libie_aq_desc)),
I40E_ADMINQ_DESC_ALIGNMENT);
return ret_code;
@ -80,7 +80,7 @@ static void i40e_free_adminq_arq(struct i40e_hw *hw)
**/
static int i40e_alloc_arq_bufs(struct i40e_hw *hw)
{
struct i40e_aq_desc *desc;
struct libie_aq_desc *desc;
struct i40e_dma_mem *bi;
int ret_code;
int i;
@ -108,9 +108,9 @@ static int i40e_alloc_arq_bufs(struct i40e_hw *hw)
/* now configure the descriptors for use */
desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF);
if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB);
desc->opcode = 0;
/* This is in accordance with Admin queue design, there is no
* register for buffer size configuration
@ -119,12 +119,12 @@ static int i40e_alloc_arq_bufs(struct i40e_hw *hw)
desc->retval = 0;
desc->cookie_high = 0;
desc->cookie_low = 0;
desc->params.external.addr_high =
desc->params.generic.addr_high =
cpu_to_le32(upper_32_bits(bi->pa));
desc->params.external.addr_low =
desc->params.generic.addr_low =
cpu_to_le32(lower_32_bits(bi->pa));
desc->params.external.param0 = 0;
desc->params.external.param1 = 0;
desc->params.generic.param0 = 0;
desc->params.generic.param1 = 0;
}
alloc_arq_bufs:
@ -691,8 +691,8 @@ static u16 i40e_clean_asq(struct i40e_hw *hw)
struct i40e_adminq_ring *asq = &(hw->aq.asq);
struct i40e_asq_cmd_details *details;
u16 ntc = asq->next_to_clean;
struct i40e_aq_desc desc_cb;
struct i40e_aq_desc *desc;
struct libie_aq_desc desc_cb;
struct libie_aq_desc *desc;
desc = I40E_ADMINQ_DESC(*asq, ntc);
details = I40E_ADMINQ_DETAILS(*asq, ntc);
@ -750,7 +750,7 @@ static bool i40e_asq_done(struct i40e_hw *hw)
**/
static int
i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,
struct i40e_aq_desc *desc,
struct libie_aq_desc *desc,
void *buff, /* can be NULL */
u16 buff_size,
struct i40e_asq_cmd_details *cmd_details,
@ -758,7 +758,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,
{
struct i40e_dma_mem *dma_buff = NULL;
struct i40e_asq_cmd_details *details;
struct i40e_aq_desc *desc_on_ring;
struct libie_aq_desc *desc_on_ring;
bool cmd_completed = false;
u16 retval = 0;
int status = 0;
@ -771,7 +771,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,
goto asq_send_command_error;
}
hw->aq.asq_last_status = I40E_AQ_RC_OK;
hw->aq.asq_last_status = LIBIE_AQ_RC_OK;
val = rd32(hw, I40E_PF_ATQH);
if (val >= hw->aq.num_asq_entries) {
@ -851,9 +851,9 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,
/* Update the address values in the desc with the pa value
* for respective buffer
*/
desc_on_ring->params.external.addr_high =
desc_on_ring->params.generic.addr_high =
cpu_to_le32(upper_32_bits(dma_buff->pa));
desc_on_ring->params.external.addr_low =
desc_on_ring->params.generic.addr_low =
cpu_to_le32(lower_32_bits(dma_buff->pa));
}
@ -905,13 +905,13 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,
retval &= 0xff;
}
cmd_completed = true;
if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
if ((enum libie_aq_err)retval == LIBIE_AQ_RC_OK)
status = 0;
else if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_EBUSY)
else if ((enum libie_aq_err)retval == LIBIE_AQ_RC_EBUSY)
status = -EBUSY;
else
status = -EIO;
hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
hw->aq.asq_last_status = (enum libie_aq_err)retval;
}
i40e_debug(hw, I40E_DEBUG_AQ_COMMAND,
@ -954,7 +954,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,
**/
int
i40e_asq_send_command_atomic(struct i40e_hw *hw,
struct i40e_aq_desc *desc,
struct libie_aq_desc *desc,
void *buff, /* can be NULL */
u16 buff_size,
struct i40e_asq_cmd_details *cmd_details,
@ -972,7 +972,7 @@ i40e_asq_send_command_atomic(struct i40e_hw *hw,
}
int
i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc,
i40e_asq_send_command(struct i40e_hw *hw, struct libie_aq_desc *desc,
void *buff, /* can be NULL */ u16 buff_size,
struct i40e_asq_cmd_details *cmd_details)
{
@ -996,12 +996,12 @@ i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc,
**/
int
i40e_asq_send_command_atomic_v2(struct i40e_hw *hw,
struct i40e_aq_desc *desc,
struct libie_aq_desc *desc,
void *buff, /* can be NULL */
u16 buff_size,
struct i40e_asq_cmd_details *cmd_details,
bool is_atomic_context,
enum i40e_admin_queue_err *aq_status)
enum libie_aq_err *aq_status)
{
int status;
@ -1023,13 +1023,13 @@ i40e_asq_send_command_atomic_v2(struct i40e_hw *hw,
*
* Fill the desc with default values
**/
void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
void i40e_fill_default_direct_cmd_desc(struct libie_aq_desc *desc,
u16 opcode)
{
/* zero out the desc */
memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
memset((void *)desc, 0, sizeof(struct libie_aq_desc));
desc->opcode = cpu_to_le16(opcode);
desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);
desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI);
}
/**
@ -1047,7 +1047,7 @@ int i40e_clean_arq_element(struct i40e_hw *hw,
u16 *pending)
{
u16 ntc = hw->aq.arq.next_to_clean;
struct i40e_aq_desc *desc;
struct libie_aq_desc *desc;
struct i40e_dma_mem *bi;
int ret_code = 0;
u16 desc_idx;
@ -1081,9 +1081,9 @@ int i40e_clean_arq_element(struct i40e_hw *hw,
desc_idx = ntc;
hw->aq.arq_last_status =
(enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
(enum libie_aq_err)le16_to_cpu(desc->retval);
flags = le16_to_cpu(desc->flags);
if (flags & I40E_AQ_FLAG_ERR) {
if (flags & LIBIE_AQ_FLAG_ERR) {
ret_code = -EIO;
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
@ -1107,14 +1107,14 @@ int i40e_clean_arq_element(struct i40e_hw *hw,
* size
*/
bi = &hw->aq.arq.r.arq_bi[ntc];
memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
memset((void *)desc, 0, sizeof(struct libie_aq_desc));
desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF);
if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB);
desc->datalen = cpu_to_le16((u16)bi->size);
desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
desc->params.generic.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
desc->params.generic.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
/* set tail = the last cleaned desc index. */
wr32(hw, I40E_PF_ARQT, ntc);

12
drivers/net/ethernet/intel/i40e/i40e_adminq.h
View File

@ -9,7 +9,7 @@
#include "i40e_adminq_cmd.h"
#define I40E_ADMINQ_DESC(R, i) \
(&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
(&(((struct libie_aq_desc *)((R).desc_buf.va))[i]))
#define I40E_ADMINQ_DESC_ALIGNMENT 4096
@ -39,7 +39,7 @@ struct i40e_asq_cmd_details {
u16 flags_dis;
bool async;
bool postpone;
struct i40e_aq_desc *wb_desc;
struct libie_aq_desc *wb_desc;
};
#define I40E_ADMINQ_DETAILS(R, i) \
@ -47,7 +47,7 @@ struct i40e_asq_cmd_details {
/* ARQ event information */
struct i40e_arq_event_info {
struct i40e_aq_desc desc;
struct libie_aq_desc desc;
u16 msg_len;
u16 buf_len;
u8 *msg_buf;
@ -72,8 +72,8 @@ struct i40e_adminq_info {
struct mutex arq_mutex; /* Receive queue lock */
/* last status values on send and receive queues */
enum i40e_admin_queue_err asq_last_status;
enum i40e_admin_queue_err arq_last_status;
enum libie_aq_err asq_last_status;
enum libie_aq_err arq_last_status;
};
/**
@ -119,7 +119,7 @@ static inline int i40e_aq_rc_to_posix(int aq_ret, int aq_rc)
#define I40E_AQ_LARGE_BUF 512
#define I40E_ASQ_CMD_TIMEOUT 250000 /* usecs */
void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
void i40e_fill_default_direct_cmd_desc(struct libie_aq_desc *desc,
u16 opcode);
#endif /* _I40E_ADMINQ_H_ */

155
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
View File

@ -4,6 +4,8 @@
#ifndef _I40E_ADMINQ_CMD_H_
#define _I40E_ADMINQ_CMD_H_
#include <linux/net/intel/libie/adminq.h>
#include <linux/bits.h>
#include <linux/types.h>
@ -30,75 +32,6 @@
/* API version 1.10 for X722 devices adds ability to request FEC encoding */
#define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
struct i40e_aq_desc {
__le16 flags;
__le16 opcode;
__le16 datalen;
__le16 retval;
__le32 cookie_high;
__le32 cookie_low;
union {
struct {
__le32 param0;
__le32 param1;
__le32 param2;
__le32 param3;
} internal;
struct {
__le32 param0;
__le32 param1;
__le32 addr_high;
__le32 addr_low;
} external;
u8 raw[16];
} params;
};
/* Flags sub-structure
* |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
* |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
*/
/* command flags and offsets*/
#define I40E_AQ_FLAG_ERR_SHIFT 2
#define I40E_AQ_FLAG_LB_SHIFT 9
#define I40E_AQ_FLAG_RD_SHIFT 10
#define I40E_AQ_FLAG_BUF_SHIFT 12
#define I40E_AQ_FLAG_SI_SHIFT 13
#define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
#define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
#define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
#define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
#define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
/* error codes */
enum i40e_admin_queue_err {
I40E_AQ_RC_OK = 0, /* success */
I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
I40E_AQ_RC_ENOENT = 2, /* No such element */
I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
I40E_AQ_RC_EINTR = 4, /* operation interrupted */
I40E_AQ_RC_EIO = 5, /* I/O error */
I40E_AQ_RC_ENXIO = 6, /* No such resource */
I40E_AQ_RC_E2BIG = 7, /* Arg too long */
I40E_AQ_RC_EAGAIN = 8, /* Try again */
I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
I40E_AQ_RC_EACCES = 10, /* Permission denied */
I40E_AQ_RC_EFAULT = 11, /* Bad address */
I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
I40E_AQ_RC_EEXIST = 13, /* object already exists */
I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
I40E_AQ_RC_EFBIG = 22, /* File too large */
};
/* Admin Queue command opcodes */
enum i40e_admin_queue_opc {
/* aq commands */
@ -320,21 +253,6 @@ struct i40e_aqc_get_version {
__le16 api_minor;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
/* Send driver version (indirect 0x0002) */
struct i40e_aqc_driver_version {
u8 driver_major_ver;
u8 driver_minor_ver;
u8 driver_build_ver;
u8 driver_subbuild_ver;
u8 reserved[4];
__le32 address_high;
__le32 address_low;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
/* Queue Shutdown (direct 0x0003) */
struct i40e_aqc_queue_shutdown {
__le32 driver_unloading;
@ -352,75 +270,6 @@ struct i40e_aqc_set_pf_context {
I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
/* Request resource ownership (direct 0x0008)
* Release resource ownership (direct 0x0009)
*/
struct i40e_aqc_request_resource {
__le16 resource_id;
__le16 access_type;
__le32 timeout;
__le32 resource_number;
u8 reserved[4];
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
/* Get function capabilities (indirect 0x000A)
* Get device capabilities (indirect 0x000B)
*/
struct i40e_aqc_list_capabilites {
u8 command_flags;
u8 pf_index;
u8 reserved[2];
__le32 count;
__le32 addr_high;
__le32 addr_low;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
struct i40e_aqc_list_capabilities_element_resp {
__le16 id;
u8 major_rev;
u8 minor_rev;
__le32 number;
__le32 logical_id;
__le32 phys_id;
u8 reserved[16];
};
/* list of caps */
#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
#define I40E_AQ_CAP_ID_SRIOV 0x0012
#define I40E_AQ_CAP_ID_VF 0x0013
#define I40E_AQ_CAP_ID_VMDQ 0x0014
#define I40E_AQ_CAP_ID_8021QBG 0x0015
#define I40E_AQ_CAP_ID_8021QBR 0x0016
#define I40E_AQ_CAP_ID_VSI 0x0017
#define I40E_AQ_CAP_ID_DCB 0x0018
#define I40E_AQ_CAP_ID_FCOE 0x0021
#define I40E_AQ_CAP_ID_ISCSI 0x0022
#define I40E_AQ_CAP_ID_RSS 0x0040
#define I40E_AQ_CAP_ID_RXQ 0x0041
#define I40E_AQ_CAP_ID_TXQ 0x0042
#define I40E_AQ_CAP_ID_MSIX 0x0043
#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
#define I40E_AQ_CAP_ID_1588 0x0046
#define I40E_AQ_CAP_ID_IWARP 0x0051
#define I40E_AQ_CAP_ID_LED 0x0061
#define I40E_AQ_CAP_ID_SDP 0x0062
#define I40E_AQ_CAP_ID_MDIO 0x0063
#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
#define I40E_AQ_CAP_ID_FLEX10 0x00F1
#define I40E_AQ_CAP_ID_CEM 0x00F2
/* Set CPPM Configuration (direct 0x0103) */
struct i40e_aqc_cppm_configuration {
__le16 command_flags;

7
drivers/net/ethernet/intel/i40e/i40e_client.c
View File

@ -682,9 +682,7 @@ static int i40e_client_update_vsi_ctxt(struct i40e_info *ldev,
if (err) {
dev_info(&pf->pdev->dev,
"couldn't get PF vsi config, err %pe aq_err %s\n",
ERR_PTR(err),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status));
return -ENOENT;
}
@ -711,8 +709,7 @@ static int i40e_client_update_vsi_ctxt(struct i40e_info *ldev,
dev_info(&pf->pdev->dev,
"update VSI ctxt for PE failed, err %pe aq_err %s\n",
ERR_PTR(err),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
}
}
return err;

730
drivers/net/ethernet/intel/i40e/i40e_common.c
View File

File diff suppressed because it is too large Load Diff

10
drivers/net/ethernet/intel/i40e/i40e_dcb.c
View File

@ -750,7 +750,7 @@ static int i40e_get_ieee_dcb_config(struct i40e_hw *hw)
I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
&hw->remote_dcbx_config);
/* Don't treat ENOENT as an error for Remote MIBs */
if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)
if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT)
ret = 0;
out:
@ -799,7 +799,7 @@ int i40e_get_dcb_config(struct i40e_hw *hw)
}
/* CEE mode not enabled try querying IEEE data */
if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)
if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT)
return i40e_get_ieee_dcb_config(hw);
if (ret)
@ -816,7 +816,7 @@ int i40e_get_dcb_config(struct i40e_hw *hw)
I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
&hw->remote_dcbx_config);
/* Don't treat ENOENT as an error for Remote MIBs */
if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)
if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT)
ret = 0;
out:
@ -925,11 +925,11 @@ i40e_get_fw_lldp_status(struct i40e_hw *hw,
if (!ret) {
*lldp_status = I40E_GET_FW_LLDP_STATUS_ENABLED;
} else if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) {
} else if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT) {
/* MIB is not available yet but the agent is running */
*lldp_status = I40E_GET_FW_LLDP_STATUS_ENABLED;
ret = 0;
} else if (hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
} else if (hw->aq.asq_last_status == LIBIE_AQ_RC_EPERM) {
*lldp_status = I40E_GET_FW_LLDP_STATUS_DISABLED;
ret = 0;
}

8
drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c
View File

@ -136,7 +136,7 @@ static int i40e_dcbnl_ieee_setets(struct net_device *netdev,
dev_info(&pf->pdev->dev,
"Failed setting DCB ETS configuration err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return -EINVAL;
}
@ -175,7 +175,7 @@ static int i40e_dcbnl_ieee_setpfc(struct net_device *netdev,
dev_info(&pf->pdev->dev,
"Failed setting DCB PFC configuration err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return -EINVAL;
}
@ -226,7 +226,7 @@ static int i40e_dcbnl_ieee_setapp(struct net_device *netdev,
dev_info(&pf->pdev->dev,
"Failed setting DCB configuration err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return -EINVAL;
}
@ -291,7 +291,7 @@ static int i40e_dcbnl_ieee_delapp(struct net_device *netdev,
dev_info(&pf->pdev->dev,
"Failed setting DCB configuration err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return -EINVAL;
}

46
drivers/net/ethernet/intel/i40e/i40e_debugfs.c
View File

@ -489,7 +489,7 @@ static void i40e_dbg_dump_aq_desc(struct i40e_pf *pf)
dev_info(&pf->pdev->dev, "AdminQ Tx Ring\n");
ring = &(hw->aq.asq);
for (i = 0; i < ring->count; i++) {
struct i40e_aq_desc *d = I40E_ADMINQ_DESC(*ring, i);
struct libie_aq_desc *d = I40E_ADMINQ_DESC(*ring, i);
dev_info(&pf->pdev->dev,
" at[%02d] flags=0x%04x op=0x%04x dlen=0x%04x ret=0x%04x cookie_h=0x%08x cookie_l=0x%08x\n",
@ -502,7 +502,7 @@ static void i40e_dbg_dump_aq_desc(struct i40e_pf *pf)
dev_info(&pf->pdev->dev, "AdminQ Rx Ring\n");
ring = &(hw->aq.arq);
for (i = 0; i < ring->count; i++) {
struct i40e_aq_desc *d = I40E_ADMINQ_DESC(*ring, i);
struct libie_aq_desc *d = I40E_ADMINQ_DESC(*ring, i);
dev_info(&pf->pdev->dev,
" ar[%02d] flags=0x%04x op=0x%04x dlen=0x%04x ret=0x%04x cookie_h=0x%08x cookie_l=0x%08x\n",
@ -1268,10 +1268,10 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
dev_info(&pf->pdev->dev, "clear_stats vsi [seid] or clear_stats port\n");
}
} else if (strncmp(cmd_buf, "send aq_cmd", 11) == 0) {
struct i40e_aq_desc *desc;
struct libie_aq_desc *desc;
int ret;
desc = kzalloc(sizeof(struct i40e_aq_desc), GFP_KERNEL);
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
if (!desc)
goto command_write_done;
cnt = sscanf(&cmd_buf[11],
@ -1279,10 +1279,10 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
&desc->flags,
&desc->opcode, &desc->datalen, &desc->retval,
&desc->cookie_high, &desc->cookie_low,
&desc->params.internal.param0,
&desc->params.internal.param1,
&desc->params.internal.param2,
&desc->params.internal.param3);
&desc->params.generic.param0,
&desc->params.generic.param1,
&desc->params.generic.addr_high,
&desc->params.generic.addr_low);
if (cnt != 10) {
dev_info(&pf->pdev->dev,
"send aq_cmd: bad command string, cnt=%d\n",
@ -1307,19 +1307,19 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
"AQ desc WB 0x%04x 0x%04x 0x%04x 0x%04x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
desc->flags, desc->opcode, desc->datalen, desc->retval,
desc->cookie_high, desc->cookie_low,
desc->params.internal.param0,
desc->params.internal.param1,
desc->params.internal.param2,
desc->params.internal.param3);
desc->params.generic.param0,
desc->params.generic.param1,
desc->params.generic.addr_high,
desc->params.generic.addr_low);
kfree(desc);
desc = NULL;
} else if (strncmp(cmd_buf, "send indirect aq_cmd", 20) == 0) {
struct i40e_aq_desc *desc;
struct libie_aq_desc *desc;
u16 buffer_len;
u8 *buff;
int ret;
desc = kzalloc(sizeof(struct i40e_aq_desc), GFP_KERNEL);
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
if (!desc)
goto command_write_done;
cnt = sscanf(&cmd_buf[20],
@ -1327,10 +1327,10 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
&desc->flags,
&desc->opcode, &desc->datalen, &desc->retval,
&desc->cookie_high, &desc->cookie_low,
&desc->params.internal.param0,
&desc->params.internal.param1,
&desc->params.internal.param2,
&desc->params.internal.param3,
&desc->params.generic.param0,
&desc->params.generic.param1,
&desc->params.generic.addr_high,
&desc->params.generic.addr_low,
&buffer_len);
if (cnt != 11) {
dev_info(&pf->pdev->dev,
@ -1350,7 +1350,7 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
desc = NULL;
goto command_write_done;
}
desc->flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
desc->flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF);
ret = i40e_asq_send_command(&pf->hw, desc, buff,
buffer_len, NULL);
if (!ret) {
@ -1368,10 +1368,10 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
"AQ desc WB 0x%04x 0x%04x 0x%04x 0x%04x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
desc->flags, desc->opcode, desc->datalen, desc->retval,
desc->cookie_high, desc->cookie_low,
desc->params.internal.param0,
desc->params.internal.param1,
desc->params.internal.param2,
desc->params.internal.param3);
desc->params.generic.param0,
desc->params.generic.param1,
desc->params.generic.addr_high,
desc->params.generic.addr_low);
print_hex_dump(KERN_INFO, "AQ buffer WB: ",
DUMP_PREFIX_OFFSET, 16, 1,
buff, buffer_len, true);

36
drivers/net/ethernet/intel/i40e/i40e_ethtool.c
View File

@ -1462,7 +1462,7 @@ static int i40e_set_link_ksettings(struct net_device *netdev,
netdev_info(netdev,
"Set phy config failed, err %pe aq_err %s\n",
ERR_PTR(status),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
err = -EAGAIN;
goto done;
}
@ -1472,7 +1472,7 @@ static int i40e_set_link_ksettings(struct net_device *netdev,
netdev_dbg(netdev,
"Updating link info failed with err %pe aq_err %s\n",
ERR_PTR(status),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
} else {
netdev_info(netdev, "Nothing changed, exiting without setting anything.\n");
@ -1520,7 +1520,7 @@ static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)
netdev_info(netdev,
"Set phy config failed, err %pe aq_err %s\n",
ERR_PTR(status),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
err = -EAGAIN;
goto done;
}
@ -1534,7 +1534,7 @@ static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)
netdev_dbg(netdev,
"Updating link info failed with err %pe aq_err %s\n",
ERR_PTR(status),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
}
done:
@ -1641,7 +1641,7 @@ static int i40e_nway_reset(struct net_device *netdev)
if (ret) {
netdev_info(netdev, "link restart failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
return -EIO;
}
@ -1758,19 +1758,19 @@ static int i40e_set_pauseparam(struct net_device *netdev,
if (aq_failures & I40E_SET_FC_AQ_FAIL_GET) {
netdev_info(netdev, "Set fc failed on the get_phy_capabilities call with err %pe aq_err %s\n",
ERR_PTR(status),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
err = -EAGAIN;
}
if (aq_failures & I40E_SET_FC_AQ_FAIL_SET) {
netdev_info(netdev, "Set fc failed on the set_phy_config call with err %pe aq_err %s\n",
ERR_PTR(status),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
err = -EAGAIN;
}
if (aq_failures & I40E_SET_FC_AQ_FAIL_UPDATE) {
netdev_info(netdev, "Set fc failed on the get_link_info call with err %pe aq_err %s\n",
ERR_PTR(status),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
err = -EAGAIN;
}
@ -1918,13 +1918,13 @@ static int i40e_get_eeprom(struct net_device *netdev,
ret_val = i40e_aq_read_nvm(hw, 0x0, offset, len,
(u8 *)eeprom_buff + (I40E_NVM_SECTOR_SIZE * i),
last, NULL);
if (ret_val && hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
if (ret_val && hw->aq.asq_last_status == LIBIE_AQ_RC_EPERM) {
dev_info(&pf->pdev->dev,
"read NVM failed, invalid offset 0x%x\n",
offset);
break;
} else if (ret_val &&
hw->aq.asq_last_status == I40E_AQ_RC_EACCES) {
hw->aq.asq_last_status == LIBIE_AQ_RC_EACCES) {
dev_info(&pf->pdev->dev,
"read NVM failed, access, offset 0x%x\n",
offset);
@ -5249,9 +5249,9 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
DECLARE_BITMAP(orig_flags, I40E_PF_FLAGS_NBITS);
DECLARE_BITMAP(new_flags, I40E_PF_FLAGS_NBITS);
struct i40e_netdev_priv *np = netdev_priv(dev);
enum i40e_admin_queue_err adq_err;
struct i40e_vsi *vsi = np->vsi;
struct i40e_pf *pf = vsi->back;
enum libie_aq_err adq_err;
u32 reset_needed = 0;
int status;
u32 i, j;
@ -5371,12 +5371,11 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
ret = i40e_aq_set_switch_config(&pf->hw, sw_flags, valid_flags,
0, NULL);
if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
if (ret && pf->hw.aq.asq_last_status != LIBIE_AQ_RC_ESRCH) {
dev_info(&pf->pdev->dev,
"couldn't set switch config bits, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
/* not a fatal problem, just keep going */
}
}
@ -5438,16 +5437,16 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
if (status) {
adq_err = pf->hw.aq.asq_last_status;
switch (adq_err) {
case I40E_AQ_RC_EEXIST:
case LIBIE_AQ_RC_EEXIST:
dev_warn(&pf->pdev->dev,
"FW LLDP agent is already running\n");
reset_needed = 0;
break;
case I40E_AQ_RC_EPERM:
case LIBIE_AQ_RC_EPERM:
dev_warn(&pf->pdev->dev,
"Device configuration forbids SW from starting the LLDP agent.\n");
return -EINVAL;
case I40E_AQ_RC_EAGAIN:
case LIBIE_AQ_RC_EAGAIN:
dev_warn(&pf->pdev->dev,
"Stop FW LLDP agent command is still being processed, please try again in a second.\n");
return -EBUSY;
@ -5455,8 +5454,7 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
dev_warn(&pf->pdev->dev,
"Starting FW LLDP agent failed: error: %pe, %s\n",
ERR_PTR(status),
i40e_aq_str(&pf->hw,
adq_err));
libie_aq_str(adq_err));
return -EINVAL;
}
}

240
drivers/net/ethernet/intel/i40e/i40e_main.c
View File

@ -101,6 +101,7 @@ MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all), Debug mask (0x8XXXXXXX
MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
MODULE_IMPORT_NS("LIBIE");
MODULE_IMPORT_NS("LIBIE_ADMINQ");
MODULE_LICENSE("GPL v2");
static struct workqueue_struct *i40e_wq;
@ -1814,7 +1815,7 @@ static int i40e_set_mac(struct net_device *netdev, void *p)
if (ret)
netdev_info(netdev, "Ignoring error from firmware on LAA update, status %pe, AQ ret %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
}
/* schedule our worker thread which will take care of
@ -1846,7 +1847,7 @@ static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
dev_info(&pf->pdev->dev,
"Cannot set RSS key, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
return ret;
}
}
@ -1858,7 +1859,7 @@ static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
dev_info(&pf->pdev->dev,
"Cannot set RSS lut, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
return ret;
}
}
@ -2340,19 +2341,18 @@ void i40e_aqc_del_filters(struct i40e_vsi *vsi, const char *vsi_name,
int num_del, int *retval)
{
struct i40e_hw *hw = &vsi->back->hw;
enum i40e_admin_queue_err aq_status;
enum libie_aq_err aq_status;
int aq_ret;
aq_ret = i40e_aq_remove_macvlan_v2(hw, vsi->seid, list, num_del, NULL,
&aq_status);
/* Explicitly ignore and do not report when firmware returns ENOENT */
if (aq_ret && !(aq_status == I40E_AQ_RC_ENOENT)) {
if (aq_ret && !(aq_status == LIBIE_AQ_RC_ENOENT)) {
*retval = -EIO;
dev_info(&vsi->back->pdev->dev,
"ignoring delete macvlan error on %s, err %pe, aq_err %s\n",
vsi_name, ERR_PTR(aq_ret),
i40e_aq_str(hw, aq_status));
vsi_name, ERR_PTR(aq_ret), libie_aq_str(aq_status));
}
}
@ -2375,7 +2375,7 @@ void i40e_aqc_add_filters(struct i40e_vsi *vsi, const char *vsi_name,
int num_add)
{
struct i40e_hw *hw = &vsi->back->hw;
enum i40e_admin_queue_err aq_status;
enum libie_aq_err aq_status;
int fcnt;
i40e_aq_add_macvlan_v2(hw, vsi->seid, list, num_add, NULL, &aq_status);
@ -2386,19 +2386,17 @@ void i40e_aqc_add_filters(struct i40e_vsi *vsi, const char *vsi_name,
set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
dev_warn(&vsi->back->pdev->dev,
"Error %s adding RX filters on %s, promiscuous mode forced on\n",
i40e_aq_str(hw, aq_status), vsi_name);
libie_aq_str(aq_status), vsi_name);
} else if (vsi->type == I40E_VSI_SRIOV ||
vsi->type == I40E_VSI_VMDQ1 ||
vsi->type == I40E_VSI_VMDQ2) {
dev_warn(&vsi->back->pdev->dev,
"Error %s adding RX filters on %s, please set promiscuous on manually for %s\n",
i40e_aq_str(hw, aq_status), vsi_name,
vsi_name);
libie_aq_str(aq_status), vsi_name, vsi_name);
} else {
dev_warn(&vsi->back->pdev->dev,
"Error %s adding RX filters on %s, incorrect VSI type: %i.\n",
i40e_aq_str(hw, aq_status), vsi_name,
vsi->type);
libie_aq_str(aq_status), vsi_name, vsi->type);
}
}
}
@ -2441,8 +2439,7 @@ i40e_aqc_broadcast_filter(struct i40e_vsi *vsi, const char *vsi_name,
set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
dev_warn(&vsi->back->pdev->dev,
"Error %s, forcing overflow promiscuous on %s\n",
i40e_aq_str(hw, hw->aq.asq_last_status),
vsi_name);
libie_aq_str(hw->aq.asq_last_status), vsi_name);
}
return aq_ret;
@ -2483,7 +2480,7 @@ static int i40e_set_promiscuous(struct i40e_pf *pf, bool promisc)
dev_info(&pf->pdev->dev,
"Set default VSI failed, err %pe, aq_err %s\n",
ERR_PTR(aq_ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
}
} else {
aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
@ -2495,7 +2492,7 @@ static int i40e_set_promiscuous(struct i40e_pf *pf, bool promisc)
dev_info(&pf->pdev->dev,
"set unicast promisc failed, err %pe, aq_err %s\n",
ERR_PTR(aq_ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
}
aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
hw,
@ -2505,7 +2502,7 @@ static int i40e_set_promiscuous(struct i40e_pf *pf, bool promisc)
dev_info(&pf->pdev->dev,
"set multicast promisc failed, err %pe, aq_err %s\n",
ERR_PTR(aq_ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
}
}
@ -2813,7 +2810,7 @@ int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
"set multi promisc failed on %s, err %pe aq_err %s\n",
vsi_name,
ERR_PTR(aq_ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
} else {
dev_info(&pf->pdev->dev, "%s allmulti mode.\n",
cur_multipromisc ? "entering" : "leaving");
@ -2834,7 +2831,7 @@ int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
cur_promisc ? "on" : "off",
vsi_name,
ERR_PTR(aq_ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
}
}
out:
@ -2983,8 +2980,7 @@ void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
dev_info(&vsi->back->pdev->dev,
"update vlan stripping failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&vsi->back->hw,
vsi->back->hw.aq.asq_last_status));
libie_aq_str(vsi->back->hw.aq.asq_last_status));
}
}
@ -3018,8 +3014,7 @@ void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
dev_info(&vsi->back->pdev->dev,
"update vlan stripping failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&vsi->back->hw,
vsi->back->hw.aq.asq_last_status));
libie_aq_str(vsi->back->hw.aq.asq_last_status));
}
}
@ -3263,8 +3258,7 @@ int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
dev_info(&vsi->back->pdev->dev,
"add pvid failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&vsi->back->hw,
vsi->back->hw.aq.asq_last_status));
libie_aq_str(vsi->back->hw.aq.asq_last_status));
return -ENOENT;
}
@ -5534,7 +5528,7 @@ static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
dev_info(&pf->pdev->dev,
"couldn't get PF vsi bw config, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return -EINVAL;
}
@ -5545,7 +5539,7 @@ static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
dev_info(&pf->pdev->dev,
"couldn't get PF vsi ets bw config, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return -EINVAL;
}
@ -5735,7 +5729,7 @@ int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset)
if (ret) {
dev_info(&pf->pdev->dev, "Update vsi config failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
return ret;
}
/* update the local VSI info with updated queue map */
@ -5791,7 +5785,7 @@ static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
dev_info(&pf->pdev->dev,
"Failed querying vsi bw info, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
goto out;
}
if ((bw_config.tc_valid_bits & enabled_tc) != enabled_tc) {
@ -5858,7 +5852,7 @@ static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
dev_info(&pf->pdev->dev,
"Update vsi tc config failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
goto out;
}
/* update the local VSI info with updated queue map */
@ -5871,7 +5865,7 @@ static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
dev_info(&pf->pdev->dev,
"Failed updating vsi bw info, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
goto out;
}
@ -5985,7 +5979,7 @@ int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate)
dev_err(&pf->pdev->dev,
"Failed set tx rate (%llu Mbps) for vsi->seid %u, err %pe aq_err %s\n",
max_tx_rate, seid, ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return ret;
}
@ -5997,8 +5991,8 @@ int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate)
**/
static void i40e_remove_queue_channels(struct i40e_vsi *vsi)
{
enum i40e_admin_queue_err last_aq_status;
struct i40e_cloud_filter *cfilter;
enum libie_aq_err last_aq_status;
struct i40e_channel *ch, *ch_tmp;
struct i40e_pf *pf = vsi->back;
struct hlist_node *node;
@ -6061,7 +6055,7 @@ static void i40e_remove_queue_channels(struct i40e_vsi *vsi)
dev_info(&pf->pdev->dev,
"Failed to delete cloud filter, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, last_aq_status));
libie_aq_str(last_aq_status));
kfree(cfilter);
}
@ -6196,7 +6190,7 @@ static int i40e_vsi_reconfig_rss(struct i40e_vsi *vsi, u16 rss_size)
dev_info(&pf->pdev->dev,
"Cannot set RSS lut, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
kfree(lut);
return ret;
}
@ -6295,8 +6289,7 @@ static int i40e_add_channel(struct i40e_pf *pf, u16 uplink_seid,
dev_info(&pf->pdev->dev,
"add new vsi failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return -ENOENT;
}
@ -6539,12 +6532,10 @@ static int i40e_validate_and_set_switch_mode(struct i40e_vsi *vsi)
ret = i40e_aq_set_switch_config(hw, pf->last_sw_conf_flags,
pf->last_sw_conf_valid_flags,
mode, NULL);
if (ret && hw->aq.asq_last_status != I40E_AQ_RC_ESRCH)
if (ret && hw->aq.asq_last_status != LIBIE_AQ_RC_ESRCH)
dev_err(&pf->pdev->dev,
"couldn't set switch config bits, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw,
hw->aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status));
return ret;
}
@ -6743,8 +6734,7 @@ int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
if (ret) {
dev_info(&pf->pdev->dev,
"VEB bw config failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
goto out;
}
@ -6753,8 +6743,7 @@ int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
if (ret) {
dev_info(&pf->pdev->dev,
"Failed getting veb bw config, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
}
out:
@ -6835,7 +6824,7 @@ static int i40e_resume_port_tx(struct i40e_pf *pf)
dev_info(&pf->pdev->dev,
"Resume Port Tx failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
/* Schedule PF reset to recover */
set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
i40e_service_event_schedule(pf);
@ -6859,8 +6848,7 @@ static int i40e_suspend_port_tx(struct i40e_pf *pf)
if (ret) {
dev_info(&pf->pdev->dev,
"Suspend Port Tx failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
/* Schedule PF reset to recover */
set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
i40e_service_event_schedule(pf);
@ -6899,8 +6887,7 @@ static int i40e_hw_set_dcb_config(struct i40e_pf *pf,
if (ret) {
dev_info(&pf->pdev->dev,
"Set DCB Config failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
goto out;
}
@ -7016,8 +7003,7 @@ int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg)
if (ret) {
dev_info(&pf->pdev->dev,
"Modify Port ETS failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
goto out;
}
@ -7056,8 +7042,7 @@ int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg)
if (ret) {
dev_info(&pf->pdev->dev,
"DCB Updated failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
goto out;
}
@ -7140,8 +7125,7 @@ int i40e_dcb_sw_default_config(struct i40e_pf *pf)
if (err) {
dev_info(&pf->pdev->dev,
"Enable Port ETS failed, err %pe aq_err %s\n",
ERR_PTR(err),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status));
err = -ENOENT;
goto out;
}
@ -7214,14 +7198,13 @@ static int i40e_init_pf_dcb(struct i40e_pf *pf)
dev_dbg(&pf->pdev->dev,
"DCBX offload is supported for this PF.\n");
}
} else if (pf->hw.aq.asq_last_status == I40E_AQ_RC_EPERM) {
} else if (pf->hw.aq.asq_last_status == LIBIE_AQ_RC_EPERM) {
dev_info(&pf->pdev->dev, "FW LLDP disabled for this PF.\n");
set_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags);
} else {
dev_info(&pf->pdev->dev,
"Query for DCB configuration failed, err %pe aq_err %s\n",
ERR_PTR(err),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status));
}
out:
@ -7477,8 +7460,7 @@ static int i40e_force_link_state(struct i40e_pf *pf, bool is_up)
if (err) {
dev_err(&pf->pdev->dev,
"failed to get phy cap., ret = %pe last_status = %s\n",
ERR_PTR(err),
i40e_aq_str(hw, hw->aq.asq_last_status));
ERR_PTR(err), libie_aq_str(hw->aq.asq_last_status));
return err;
}
speed = abilities.link_speed;
@ -7489,8 +7471,7 @@ static int i40e_force_link_state(struct i40e_pf *pf, bool is_up)
if (err) {
dev_err(&pf->pdev->dev,
"failed to get phy cap., ret = %pe last_status = %s\n",
ERR_PTR(err),
i40e_aq_str(hw, hw->aq.asq_last_status));
ERR_PTR(err), libie_aq_str(hw->aq.asq_last_status));
return err;
}
@ -7534,8 +7515,7 @@ static int i40e_force_link_state(struct i40e_pf *pf, bool is_up)
if (err) {
dev_err(&pf->pdev->dev,
"set phy config ret = %pe last_status = %s\n",
ERR_PTR(err),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status));
return err;
}
@ -7875,8 +7855,7 @@ static int i40e_fwd_ring_up(struct i40e_vsi *vsi, struct net_device *vdev,
}
dev_info(&pf->pdev->dev,
"Error adding mac filter on macvlan err %pe, aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, aq_err));
ERR_PTR(ret), libie_aq_str(aq_err));
netdev_err(vdev, "L2fwd offload disabled to L2 filter error\n");
}
@ -7948,8 +7927,7 @@ static int i40e_setup_macvlans(struct i40e_vsi *vsi, u16 macvlan_cnt, u16 qcnt,
if (ret) {
dev_info(&pf->pdev->dev,
"Update vsi tc config failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status));
return ret;
}
/* update the local VSI info with updated queue map */
@ -8164,8 +8142,7 @@ static void i40e_fwd_del(struct net_device *netdev, void *vdev)
} else {
dev_info(&pf->pdev->dev,
"Error deleting mac filter on macvlan err %pe, aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, aq_err));
ERR_PTR(ret), libie_aq_str(aq_err));
}
break;
}
@ -9419,8 +9396,7 @@ bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
static int i40e_handle_lldp_event(struct i40e_pf *pf,
struct i40e_arq_event_info *e)
{
struct i40e_aqc_lldp_get_mib *mib =
(struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
struct i40e_aqc_lldp_get_mib *mib = libie_aq_raw(&e->desc);
struct i40e_hw *hw = &pf->hw;
struct i40e_dcbx_config tmp_dcbx_cfg;
bool need_reconfig = false;
@ -9477,8 +9453,7 @@ static int i40e_handle_lldp_event(struct i40e_pf *pf,
dev_info(&pf->pdev->dev,
"Failed querying DCB configuration data from firmware, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
}
goto exit;
}
@ -9559,8 +9534,7 @@ void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
struct i40e_arq_event_info *e)
{
struct i40e_aqc_lan_overflow *data =
(struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
struct i40e_aqc_lan_overflow *data = libie_aq_raw(&e->desc);
u32 queue = le32_to_cpu(data->prtdcb_rupto);
u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
struct i40e_hw *hw = &pf->hw;
@ -10080,8 +10054,7 @@ static void i40e_reset_subtask(struct i40e_pf *pf)
static void i40e_handle_link_event(struct i40e_pf *pf,
struct i40e_arq_event_info *e)
{
struct i40e_aqc_get_link_status *status =
(struct i40e_aqc_get_link_status *)&e->desc.params.raw;
struct i40e_aqc_get_link_status *status = libie_aq_raw(&e->desc);
/* Do a new status request to re-enable LSE reporting
* and load new status information into the hw struct
@ -10289,8 +10262,7 @@ static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
if (ret) {
dev_info(&pf->pdev->dev,
"couldn't get PF vsi config, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
return;
}
ctxt.flags = I40E_AQ_VSI_TYPE_PF;
@ -10301,8 +10273,7 @@ static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
if (ret) {
dev_info(&pf->pdev->dev,
"update vsi switch failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
}
}
@ -10325,8 +10296,7 @@ static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
if (ret) {
dev_info(&pf->pdev->dev,
"couldn't get PF vsi config, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
return;
}
ctxt.flags = I40E_AQ_VSI_TYPE_PF;
@ -10337,8 +10307,7 @@ static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
if (ret) {
dev_info(&pf->pdev->dev,
"update vsi switch failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
}
}
@ -10453,12 +10422,12 @@ static int i40e_reconstitute_veb(struct i40e_veb *veb)
static int i40e_get_capabilities(struct i40e_pf *pf,
enum i40e_admin_queue_opc list_type)
{
struct i40e_aqc_list_capabilities_element_resp *cap_buf;
struct libie_aqc_list_caps_elem *cap_buf;
u16 data_size;
int buf_len;
int err;
buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
buf_len = 40 * sizeof(struct libie_aqc_list_caps_elem);
do {
cap_buf = kzalloc(buf_len, GFP_KERNEL);
if (!cap_buf)
@ -10471,15 +10440,14 @@ static int i40e_get_capabilities(struct i40e_pf *pf,
/* data loaded, buffer no longer needed */
kfree(cap_buf);
if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
if (pf->hw.aq.asq_last_status == LIBIE_AQ_RC_ENOMEM) {
/* retry with a larger buffer */
buf_len = data_size;
} else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK || err) {
} else if (pf->hw.aq.asq_last_status != LIBIE_AQ_RC_OK || err) {
dev_info(&pf->pdev->dev,
"capability discovery failed, err %pe aq_err %s\n",
ERR_PTR(err),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return -ENODEV;
}
} while (err);
@ -10616,8 +10584,7 @@ static int i40e_rebuild_cloud_filters(struct i40e_vsi *vsi, u16 seid)
dev_dbg(&pf->pdev->dev,
"Failed to rebuild cloud filter, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return ret;
}
}
@ -10858,8 +10825,7 @@ static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired)
ret = i40e_init_adminq(&pf->hw);
if (ret) {
dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
goto clear_recovery;
}
i40e_get_oem_version(&pf->hw);
@ -10970,8 +10936,7 @@ static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired)
I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
if (ret)
dev_info(&pf->pdev->dev, "set phy mask fail, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
/* Rebuild the VSIs and VEBs that existed before reset.
* They are still in our local switch element arrays, so only
@ -11069,8 +11034,7 @@ static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired)
if (ret)
dev_info(&pf->pdev->dev, "link restart failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
}
/* reinit the misc interrupt */
if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) {
@ -11101,8 +11065,7 @@ static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired)
dev_warn(&pf->pdev->dev,
"Failed to restore promiscuous setting: %s, err %pe aq_err %s\n",
pf->cur_promisc ? "on" : "off",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
i40e_reset_all_vfs(pf, true);
@ -12308,8 +12271,7 @@ static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
dev_info(&pf->pdev->dev,
"Cannot get RSS key, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return ret;
}
}
@ -12322,8 +12284,7 @@ static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
dev_info(&pf->pdev->dev,
"Cannot get RSS lut, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return ret;
}
}
@ -12984,8 +12945,7 @@ static int i40e_udp_tunnel_set_port(struct net_device *netdev,
NULL);
if (ret) {
netdev_info(netdev, "add UDP port failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status));
return -EIO;
}
@ -13004,8 +12964,7 @@ static int i40e_udp_tunnel_unset_port(struct net_device *netdev,
ret = i40e_aq_del_udp_tunnel(hw, ti->hw_priv, NULL);
if (ret) {
netdev_info(netdev, "delete UDP port failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status));
return -EIO;
}
@ -13895,8 +13854,7 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)
dev_info(&pf->pdev->dev,
"couldn't get PF vsi config, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
return -ENOENT;
}
vsi->info = ctxt.info;
@ -13925,8 +13883,7 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)
dev_info(&pf->pdev->dev,
"update vsi failed, err %d aq_err %s\n",
ret,
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
ret = -ENOENT;
goto err;
}
@ -13945,8 +13902,7 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)
dev_info(&pf->pdev->dev,
"update vsi failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
ret = -ENOENT;
goto err;
}
@ -13969,8 +13925,7 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)
"failed to configure TCs for main VSI tc_map 0x%08x, err %pe aq_err %s\n",
enabled_tc,
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
}
}
break;
@ -14064,8 +14019,7 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)
dev_info(&vsi->back->pdev->dev,
"add vsi failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
ret = -ENOENT;
goto err;
}
@ -14095,8 +14049,7 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)
if (ret) {
dev_info(&pf->pdev->dev,
"couldn't get vsi bw info, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
/* VSI is already added so not tearing that up */
ret = 0;
}
@ -14544,8 +14497,7 @@ static int i40e_veb_get_bw_info(struct i40e_veb *veb)
if (ret) {
dev_info(&pf->pdev->dev,
"query veb bw config failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status));
goto out;
}
@ -14554,8 +14506,7 @@ static int i40e_veb_get_bw_info(struct i40e_veb *veb)
if (ret) {
dev_info(&pf->pdev->dev,
"query veb bw ets config failed, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status));
goto out;
}
@ -14743,8 +14694,7 @@ static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
if (ret) {
dev_info(&pf->pdev->dev,
"couldn't add VEB, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
return -EPERM;
}
@ -14754,16 +14704,14 @@ static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
if (ret) {
dev_info(&pf->pdev->dev,
"couldn't get VEB statistics idx, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
return -EPERM;
}
ret = i40e_veb_get_bw_info(veb);
if (ret) {
dev_info(&pf->pdev->dev,
"couldn't get VEB bw info, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
return -ENOENT;
}
@ -14958,9 +14906,7 @@ int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
if (ret) {
dev_info(&pf->pdev->dev,
"get switch config failed err %d aq_err %s\n",
ret,
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
ret, libie_aq_str(pf->hw.aq.asq_last_status));
kfree(aq_buf);
return -ENOENT;
}
@ -15005,8 +14951,7 @@ static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit, bool lock_acqui
if (ret) {
dev_info(&pf->pdev->dev,
"couldn't fetch switch config, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status));
return ret;
}
i40e_pf_reset_stats(pf);
@ -15029,12 +14974,11 @@ static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit, bool lock_acqui
valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, 0,
NULL);
if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
if (ret && pf->hw.aq.asq_last_status != LIBIE_AQ_RC_ESRCH) {
dev_info(&pf->pdev->dev,
"couldn't set switch config bits, err %pe aq_err %s\n",
ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
/* not a fatal problem, just keep going */
}
pf->last_sw_conf_valid_flags = valid_flags;
@ -15936,8 +15880,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
if (err)
dev_info(&pf->pdev->dev, "set phy mask fail, err %pe aq_err %s\n",
ERR_PTR(err),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status));
/* VF MDD event logs are rate limited to one second intervals */
ratelimit_state_init(&pf->mdd_message_rate_limit, 1 * HZ, 1);
@ -15959,8 +15902,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
if (err)
dev_info(&pf->pdev->dev, "link restart failed, err %pe aq_err %s\n",
ERR_PTR(err),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
}
/* The main driver is (mostly) up and happy. We need to set this state
* before setting up the misc vector or we get a race and the vector
@ -16091,8 +16033,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
if (err)
dev_dbg(&pf->pdev->dev, "get requested speeds ret = %pe last_status = %s\n",
ERR_PTR(err),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status));
pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
/* set the FEC config due to the board capabilities */
@ -16102,8 +16043,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
if (err)
dev_dbg(&pf->pdev->dev, "get supported phy types ret = %pe last_status = %s\n",
ERR_PTR(err),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status));
/* make sure the MFS hasn't been set lower than the default */
#define MAX_FRAME_SIZE_DEFAULT 0x2600

18
drivers/net/ethernet/intel/i40e/i40e_nvm.c
View File

@ -997,7 +997,7 @@ static int i40e_nvmupd_exec_aq(struct i40e_hw *hw,
u8 *bytes, int *perrno)
{
struct i40e_asq_cmd_details cmd_details;
struct i40e_aq_desc *aq_desc;
struct libie_aq_desc *aq_desc;
u32 buff_size = 0;
u8 *buff = NULL;
u32 aq_desc_len;
@ -1011,7 +1011,7 @@ static int i40e_nvmupd_exec_aq(struct i40e_hw *hw,
memset(&cmd_details, 0, sizeof(cmd_details));
cmd_details.wb_desc = &hw->nvm_wb_desc;
aq_desc_len = sizeof(struct i40e_aq_desc);
aq_desc_len = sizeof(struct libie_aq_desc);
memset(&hw->nvm_wb_desc, 0, aq_desc_len);
/* get the aq descriptor */
@ -1022,7 +1022,7 @@ static int i40e_nvmupd_exec_aq(struct i40e_hw *hw,
*perrno = -EINVAL;
return -EINVAL;
}
aq_desc = (struct i40e_aq_desc *)bytes;
aq_desc = (struct libie_aq_desc *)bytes;
/* if data buffer needed, make sure it's ready */
aq_data_len = cmd->data_size - aq_desc_len;
@ -1053,7 +1053,7 @@ static int i40e_nvmupd_exec_aq(struct i40e_hw *hw,
i40e_debug(hw, I40E_DEBUG_NVM,
"%s err %pe aq_err %s\n",
__func__, ERR_PTR(status),
i40e_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
*perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
return status;
}
@ -1087,7 +1087,7 @@ static int i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
aq_desc_len = sizeof(struct i40e_aq_desc);
aq_desc_len = sizeof(struct libie_aq_desc);
aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen);
/* check offset range */
@ -1154,7 +1154,7 @@ static int i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
aq_desc_len = sizeof(struct i40e_aq_desc);
aq_desc_len = sizeof(struct libie_aq_desc);
aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_aq_event_desc.datalen);
/* check copylength range */
@ -1442,7 +1442,7 @@ static int i40e_nvmupd_state_writing(struct i40e_hw *hw,
* so here we try to reacquire the semaphore then retry the write.
* We only do one retry, then give up.
*/
if (status && hw->aq.asq_last_status == I40E_AQ_RC_EBUSY &&
if (status && hw->aq.asq_last_status == LIBIE_AQ_RC_EBUSY &&
!retry_attempt) {
u32 old_asq_status = hw->aq.asq_last_status;
int old_status = status;
@ -1628,9 +1628,9 @@ void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw)
* @desc: AdminQ descriptor
**/
void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode,
struct i40e_aq_desc *desc)
struct libie_aq_desc *desc)
{
u32 aq_desc_len = sizeof(struct i40e_aq_desc);
u32 aq_desc_len = sizeof(struct libie_aq_desc);
if (opcode == hw->nvm_wait_opcode) {
memcpy(&hw->nvm_aq_event_desc, desc, aq_desc_len);

15
drivers/net/ethernet/intel/i40e/i40e_prototype.h
View File

@ -23,22 +23,22 @@ int i40e_clean_arq_element(struct i40e_hw *hw,
struct i40e_arq_event_info *e,
u16 *events_pending);
int
i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc,
i40e_asq_send_command(struct i40e_hw *hw, struct libie_aq_desc *desc,
void *buff, /* can be NULL */ u16 buff_size,
struct i40e_asq_cmd_details *cmd_details);
int
i40e_asq_send_command_atomic(struct i40e_hw *hw, struct i40e_aq_desc *desc,
i40e_asq_send_command_atomic(struct i40e_hw *hw, struct libie_aq_desc *desc,
void *buff, /* can be NULL */ u16 buff_size,
struct i40e_asq_cmd_details *cmd_details,
bool is_atomic_context);
int
i40e_asq_send_command_atomic_v2(struct i40e_hw *hw,
struct i40e_aq_desc *desc,
struct libie_aq_desc *desc,
void *buff, /* can be NULL */
u16 buff_size,
struct i40e_asq_cmd_details *cmd_details,
bool is_atomic_context,
enum i40e_admin_queue_err *aq_status);
enum libie_aq_err *aq_status);
/* debug function for adminq */
void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,
@ -46,7 +46,6 @@ void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,
bool i40e_check_asq_alive(struct i40e_hw *hw);
int i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);
const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err);
int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 seid,
bool pf_lut, u8 *lut, u16 lut_size);
@ -155,7 +154,7 @@ int
i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid,
struct i40e_aqc_add_macvlan_element_data *mv_list,
u16 count, struct i40e_asq_cmd_details *cmd_details,
enum i40e_admin_queue_err *aq_status);
enum libie_aq_err *aq_status);
int i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 vsi_id,
struct i40e_aqc_remove_macvlan_element_data *mv_list,
u16 count, struct i40e_asq_cmd_details *cmd_details);
@ -163,7 +162,7 @@ int
i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid,
struct i40e_aqc_remove_macvlan_element_data *mv_list,
u16 count, struct i40e_asq_cmd_details *cmd_details,
enum i40e_admin_queue_err *aq_status);
enum libie_aq_err *aq_status);
int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
@ -339,7 +338,7 @@ int i40e_nvmupd_command(struct i40e_hw *hw,
struct i40e_nvm_access *cmd,
u8 *bytes, int *errno);
void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode,
struct i40e_aq_desc *desc);
struct libie_aq_desc *desc);
void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw);
void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status);

6
drivers/net/ethernet/intel/i40e/i40e_type.h
View File

@ -24,7 +24,7 @@
/* forward declaration */
struct i40e_hw;
typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct libie_aq_desc *);
/* Data type manipulation macros. */
@ -555,8 +555,8 @@ struct i40e_hw {
/* state of nvm update process */
enum i40e_nvmupd_state nvmupd_state;
struct i40e_aq_desc nvm_wb_desc;
struct i40e_aq_desc nvm_aq_event_desc;
struct libie_aq_desc nvm_wb_desc;
struct libie_aq_desc nvm_aq_event_desc;
struct i40e_virt_mem nvm_buff;
bool nvm_release_on_done;
u16 nvm_wait_opcode;

27
drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
View File

@ -1290,9 +1290,8 @@ i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
dev_err(&pf->pdev->dev,
"VF %d failed to set multicast promiscuous mode err %pe aq_err %s\n",
vf->vf_id,
ERR_PTR(aq_ret),
i40e_aq_str(&pf->hw, aq_err));
vf->vf_id, ERR_PTR(aq_ret),
libie_aq_str(aq_err));
return aq_ret;
}
@ -1306,9 +1305,8 @@ i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
dev_err(&pf->pdev->dev,
"VF %d failed to set unicast promiscuous mode err %pe aq_err %s\n",
vf->vf_id,
ERR_PTR(aq_ret),
i40e_aq_str(&pf->hw, aq_err));
vf->vf_id, ERR_PTR(aq_ret),
libie_aq_str(aq_err));
}
return aq_ret;
@ -1323,9 +1321,8 @@ i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
dev_err(&pf->pdev->dev,
"VF %d failed to set multicast promiscuous mode err %pe aq_err %s\n",
vf->vf_id,
ERR_PTR(aq_ret),
i40e_aq_str(&pf->hw, aq_err));
vf->vf_id, ERR_PTR(aq_ret),
libie_aq_str(aq_err));
if (!aq_tmp)
aq_tmp = aq_ret;
@ -1339,9 +1336,8 @@ i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
dev_err(&pf->pdev->dev,
"VF %d failed to set unicast promiscuous mode err %pe aq_err %s\n",
vf->vf_id,
ERR_PTR(aq_ret),
i40e_aq_str(&pf->hw, aq_err));
vf->vf_id, ERR_PTR(aq_ret),
libie_aq_str(aq_err));
if (!aq_tmp)
aq_tmp = aq_ret;
@ -3748,8 +3744,7 @@ static void i40e_del_all_cloud_filters(struct i40e_vf *vf)
dev_err(&pf->pdev->dev,
"VF %d: Failed to delete cloud filter, err %pe aq_err %s\n",
vf->vf_id, ERR_PTR(ret),
i40e_aq_str(&pf->hw,
pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
hlist_del(&cfilter->cloud_node);
kfree(cfilter);
@ -3851,7 +3846,7 @@ static int i40e_vc_del_cloud_filter(struct i40e_vf *vf, u8 *msg)
dev_err(&pf->pdev->dev,
"VF %d: Failed to delete cloud filter, err %pe aq_err %s\n",
vf->vf_id, ERR_PTR(ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
goto err;
}
@ -3987,7 +3982,7 @@ static int i40e_vc_add_cloud_filter(struct i40e_vf *vf, u8 *msg)
dev_err(&pf->pdev->dev,
"VF %d: Failed to add cloud filter, err %pe aq_err %s\n",
vf->vf_id, ERR_PTR(aq_ret),
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
libie_aq_str(pf->hw.aq.asq_last_status));
goto err_free;
}

62
drivers/net/ethernet/intel/iavf/iavf_adminq.c
View File

@ -18,7 +18,7 @@ static enum iavf_status iavf_alloc_adminq_asq_ring(struct iavf_hw *hw)
ret_code = iavf_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
iavf_mem_atq_ring,
(hw->aq.num_asq_entries *
sizeof(struct iavf_aq_desc)),
sizeof(struct libie_aq_desc)),
IAVF_ADMINQ_DESC_ALIGNMENT);
if (ret_code)
return ret_code;
@ -45,7 +45,7 @@ static enum iavf_status iavf_alloc_adminq_arq_ring(struct iavf_hw *hw)
ret_code = iavf_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
iavf_mem_arq_ring,
(hw->aq.num_arq_entries *
sizeof(struct iavf_aq_desc)),
sizeof(struct libie_aq_desc)),
IAVF_ADMINQ_DESC_ALIGNMENT);
return ret_code;
@ -81,7 +81,7 @@ static void iavf_free_adminq_arq(struct iavf_hw *hw)
**/
static enum iavf_status iavf_alloc_arq_bufs(struct iavf_hw *hw)
{
struct iavf_aq_desc *desc;
struct libie_aq_desc *desc;
struct iavf_dma_mem *bi;
enum iavf_status ret_code;
int i;
@ -111,9 +111,9 @@ static enum iavf_status iavf_alloc_arq_bufs(struct iavf_hw *hw)
/* now configure the descriptors for use */
desc = IAVF_ADMINQ_DESC(hw->aq.arq, i);
desc->flags = cpu_to_le16(IAVF_AQ_FLAG_BUF);
desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF);
if (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF)
desc->flags |= cpu_to_le16(IAVF_AQ_FLAG_LB);
desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB);
desc->opcode = 0;
/* This is in accordance with Admin queue design, there is no
* register for buffer size configuration
@ -122,12 +122,12 @@ static enum iavf_status iavf_alloc_arq_bufs(struct iavf_hw *hw)
desc->retval = 0;
desc->cookie_high = 0;
desc->cookie_low = 0;
desc->params.external.addr_high =
desc->params.generic.addr_high =
cpu_to_le32(upper_32_bits(bi->pa));
desc->params.external.addr_low =
desc->params.generic.addr_low =
cpu_to_le32(lower_32_bits(bi->pa));
desc->params.external.param0 = 0;
desc->params.external.param1 = 0;
desc->params.generic.param0 = 0;
desc->params.generic.param1 = 0;
}
alloc_arq_bufs:
@ -558,8 +558,8 @@ static u16 iavf_clean_asq(struct iavf_hw *hw)
struct iavf_adminq_ring *asq = &hw->aq.asq;
struct iavf_asq_cmd_details *details;
u16 ntc = asq->next_to_clean;
struct iavf_aq_desc desc_cb;
struct iavf_aq_desc *desc;
struct libie_aq_desc desc_cb;
struct libie_aq_desc *desc;
desc = IAVF_ADMINQ_DESC(*asq, ntc);
details = IAVF_ADMINQ_DETAILS(*asq, ntc);
@ -573,7 +573,7 @@ static u16 iavf_clean_asq(struct iavf_hw *hw)
desc_cb = *desc;
cb_func(hw, &desc_cb);
}
memset((void *)desc, 0, sizeof(struct iavf_aq_desc));
memset((void *)desc, 0, sizeof(struct libie_aq_desc));
memset((void *)details, 0,
sizeof(struct iavf_asq_cmd_details));
ntc++;
@ -615,14 +615,14 @@ bool iavf_asq_done(struct iavf_hw *hw)
* queue. It runs the queue, cleans the queue, etc
**/
enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
struct iavf_aq_desc *desc,
struct libie_aq_desc *desc,
void *buff, /* can be NULL */
u16 buff_size,
struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_dma_mem *dma_buff = NULL;
struct iavf_asq_cmd_details *details;
struct iavf_aq_desc *desc_on_ring;
struct libie_aq_desc *desc_on_ring;
bool cmd_completed = false;
enum iavf_status status = 0;
u16 retval = 0;
@ -637,7 +637,7 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
goto asq_send_command_error;
}
hw->aq.asq_last_status = IAVF_AQ_RC_OK;
hw->aq.asq_last_status = LIBIE_AQ_RC_OK;
val = rd32(hw, IAVF_VF_ATQH1);
if (val >= hw->aq.num_asq_entries) {
@ -717,9 +717,9 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
/* Update the address values in the desc with the pa value
* for respective buffer
*/
desc_on_ring->params.external.addr_high =
desc_on_ring->params.generic.addr_high =
cpu_to_le32(upper_32_bits(dma_buff->pa));
desc_on_ring->params.external.addr_low =
desc_on_ring->params.generic.addr_low =
cpu_to_le32(lower_32_bits(dma_buff->pa));
}
@ -766,13 +766,13 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
retval &= 0xff;
}
cmd_completed = true;
if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_OK)
if ((enum libie_aq_err)retval == LIBIE_AQ_RC_OK)
status = 0;
else if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_EBUSY)
else if ((enum libie_aq_err)retval == LIBIE_AQ_RC_EBUSY)
status = IAVF_ERR_NOT_READY;
else
status = IAVF_ERR_ADMIN_QUEUE_ERROR;
hw->aq.asq_last_status = (enum iavf_admin_queue_err)retval;
hw->aq.asq_last_status = (enum libie_aq_err)retval;
}
iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
@ -809,12 +809,12 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
*
* Fill the desc with default values
**/
void iavf_fill_default_direct_cmd_desc(struct iavf_aq_desc *desc, u16 opcode)
void iavf_fill_default_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode)
{
/* zero out the desc */
memset((void *)desc, 0, sizeof(struct iavf_aq_desc));
memset((void *)desc, 0, sizeof(struct libie_aq_desc));
desc->opcode = cpu_to_le16(opcode);
desc->flags = cpu_to_le16(IAVF_AQ_FLAG_SI);
desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI);
}
/**
@ -832,7 +832,7 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
u16 *pending)
{
u16 ntc = hw->aq.arq.next_to_clean;
struct iavf_aq_desc *desc;
struct libie_aq_desc *desc;
enum iavf_status ret_code = 0;
struct iavf_dma_mem *bi;
u16 desc_idx;
@ -866,9 +866,9 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
desc_idx = ntc;
hw->aq.arq_last_status =
(enum iavf_admin_queue_err)le16_to_cpu(desc->retval);
(enum libie_aq_err)le16_to_cpu(desc->retval);
flags = le16_to_cpu(desc->flags);
if (flags & IAVF_AQ_FLAG_ERR) {
if (flags & LIBIE_AQ_FLAG_ERR) {
ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
iavf_debug(hw,
IAVF_DEBUG_AQ_MESSAGE,
@ -892,14 +892,14 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
* size
*/
bi = &hw->aq.arq.r.arq_bi[ntc];
memset((void *)desc, 0, sizeof(struct iavf_aq_desc));
memset((void *)desc, 0, sizeof(struct libie_aq_desc));
desc->flags = cpu_to_le16(IAVF_AQ_FLAG_BUF);
desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF);
if (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF)
desc->flags |= cpu_to_le16(IAVF_AQ_FLAG_LB);
desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB);
desc->datalen = cpu_to_le16((u16)bi->size);
desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
desc->params.generic.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
desc->params.generic.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
/* set tail = the last cleaned desc index. */
wr32(hw, IAVF_VF_ARQT1, ntc);

12
drivers/net/ethernet/intel/iavf/iavf_adminq.h
View File

@ -9,7 +9,7 @@
#include "iavf_adminq_cmd.h"
#define IAVF_ADMINQ_DESC(R, i) \
(&(((struct iavf_aq_desc *)((R).desc_buf.va))[i]))
(&(((struct libie_aq_desc *)((R).desc_buf.va))[i]))
#define IAVF_ADMINQ_DESC_ALIGNMENT 4096
@ -39,7 +39,7 @@ struct iavf_asq_cmd_details {
u16 flags_dis;
bool async;
bool postpone;
struct iavf_aq_desc *wb_desc;
struct libie_aq_desc *wb_desc;
};
#define IAVF_ADMINQ_DETAILS(R, i) \
@ -47,7 +47,7 @@ struct iavf_asq_cmd_details {
/* ARQ event information */
struct iavf_arq_event_info {
struct iavf_aq_desc desc;
struct libie_aq_desc desc;
u16 msg_len;
u16 buf_len;
u8 *msg_buf;
@ -72,8 +72,8 @@ struct iavf_adminq_info {
struct mutex arq_mutex; /* Receive queue lock */
/* last status values on send and receive queues */
enum iavf_admin_queue_err asq_last_status;
enum iavf_admin_queue_err arq_last_status;
enum libie_aq_err asq_last_status;
enum libie_aq_err arq_last_status;
};
/**
@ -123,6 +123,6 @@ static inline int iavf_aq_rc_to_posix(int aq_ret, int aq_rc)
#define IAVF_AQ_LARGE_BUF 512
#define IAVF_ASQ_CMD_TIMEOUT 250000 /* usecs */
void iavf_fill_default_direct_cmd_desc(struct iavf_aq_desc *desc, u16 opcode);
void iavf_fill_default_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode);
#endif /* _IAVF_ADMINQ_H_ */

83
drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h
View File

@ -4,6 +4,8 @@
#ifndef _IAVF_ADMINQ_CMD_H_
#define _IAVF_ADMINQ_CMD_H_
#include <linux/net/intel/libie/adminq.h>
/* This header file defines the iavf Admin Queue commands and is shared between
* iavf Firmware and Software.
*
@ -21,87 +23,6 @@
/* API version 1.7 implements additional link and PHY-specific APIs */
#define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
struct iavf_aq_desc {
__le16 flags;
__le16 opcode;
__le16 datalen;
__le16 retval;
__le32 cookie_high;
__le32 cookie_low;
union {
struct {
__le32 param0;
__le32 param1;
__le32 param2;
__le32 param3;
} internal;
struct {
__le32 param0;
__le32 param1;
__le32 addr_high;
__le32 addr_low;
} external;
u8 raw[16];
} params;
};
/* Flags sub-structure
* |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
* |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
*/
/* command flags and offsets*/
#define IAVF_AQ_FLAG_DD_SHIFT 0
#define IAVF_AQ_FLAG_CMP_SHIFT 1
#define IAVF_AQ_FLAG_ERR_SHIFT 2
#define IAVF_AQ_FLAG_VFE_SHIFT 3
#define IAVF_AQ_FLAG_LB_SHIFT 9
#define IAVF_AQ_FLAG_RD_SHIFT 10
#define IAVF_AQ_FLAG_VFC_SHIFT 11
#define IAVF_AQ_FLAG_BUF_SHIFT 12
#define IAVF_AQ_FLAG_SI_SHIFT 13
#define IAVF_AQ_FLAG_EI_SHIFT 14
#define IAVF_AQ_FLAG_FE_SHIFT 15
#define IAVF_AQ_FLAG_DD BIT(IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */
#define IAVF_AQ_FLAG_CMP BIT(IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */
#define IAVF_AQ_FLAG_ERR BIT(IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */
#define IAVF_AQ_FLAG_VFE BIT(IAVF_AQ_FLAG_VFE_SHIFT) /* 0x8 */
#define IAVF_AQ_FLAG_LB BIT(IAVF_AQ_FLAG_LB_SHIFT) /* 0x200 */
#define IAVF_AQ_FLAG_RD BIT(IAVF_AQ_FLAG_RD_SHIFT) /* 0x400 */
#define IAVF_AQ_FLAG_VFC BIT(IAVF_AQ_FLAG_VFC_SHIFT) /* 0x800 */
#define IAVF_AQ_FLAG_BUF BIT(IAVF_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
#define IAVF_AQ_FLAG_SI BIT(IAVF_AQ_FLAG_SI_SHIFT) /* 0x2000 */
#define IAVF_AQ_FLAG_EI BIT(IAVF_AQ_FLAG_EI_SHIFT) /* 0x4000 */
#define IAVF_AQ_FLAG_FE BIT(IAVF_AQ_FLAG_FE_SHIFT) /* 0x8000 */
/* error codes */
enum iavf_admin_queue_err {
IAVF_AQ_RC_OK = 0, /* success */
IAVF_AQ_RC_EPERM = 1, /* Operation not permitted */
IAVF_AQ_RC_ENOENT = 2, /* No such element */
IAVF_AQ_RC_ESRCH = 3, /* Bad opcode */
IAVF_AQ_RC_EINTR = 4, /* operation interrupted */
IAVF_AQ_RC_EIO = 5, /* I/O error */
IAVF_AQ_RC_ENXIO = 6, /* No such resource */
IAVF_AQ_RC_E2BIG = 7, /* Arg too long */
IAVF_AQ_RC_EAGAIN = 8, /* Try again */
IAVF_AQ_RC_ENOMEM = 9, /* Out of memory */
IAVF_AQ_RC_EACCES = 10, /* Permission denied */
IAVF_AQ_RC_EFAULT = 11, /* Bad address */
IAVF_AQ_RC_EBUSY = 12, /* Device or resource busy */
IAVF_AQ_RC_EEXIST = 13, /* object already exists */
IAVF_AQ_RC_EINVAL = 14, /* Invalid argument */
IAVF_AQ_RC_ENOTTY = 15, /* Not a typewriter */
IAVF_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
IAVF_AQ_RC_ENOSYS = 17, /* Function not implemented */
IAVF_AQ_RC_ERANGE = 18, /* Parameter out of range */
IAVF_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
IAVF_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
IAVF_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
IAVF_AQ_RC_EFBIG = 22, /* File too large */
};
/* Admin Queue command opcodes */
enum iavf_admin_queue_opc {
/* aq commands */

110
drivers/net/ethernet/intel/iavf/iavf_common.c
View File

@ -7,66 +7,6 @@
#include "iavf_adminq.h"
#include "iavf_prototype.h"
/**
* iavf_aq_str - convert AQ err code to a string
* @hw: pointer to the HW structure
* @aq_err: the AQ error code to convert
**/
const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err)
{
switch (aq_err) {
case IAVF_AQ_RC_OK:
return "OK";
case IAVF_AQ_RC_EPERM:
return "IAVF_AQ_RC_EPERM";
case IAVF_AQ_RC_ENOENT:
return "IAVF_AQ_RC_ENOENT";
case IAVF_AQ_RC_ESRCH:
return "IAVF_AQ_RC_ESRCH";
case IAVF_AQ_RC_EINTR:
return "IAVF_AQ_RC_EINTR";
case IAVF_AQ_RC_EIO:
return "IAVF_AQ_RC_EIO";
case IAVF_AQ_RC_ENXIO:
return "IAVF_AQ_RC_ENXIO";
case IAVF_AQ_RC_E2BIG:
return "IAVF_AQ_RC_E2BIG";
case IAVF_AQ_RC_EAGAIN:
return "IAVF_AQ_RC_EAGAIN";
case IAVF_AQ_RC_ENOMEM:
return "IAVF_AQ_RC_ENOMEM";
case IAVF_AQ_RC_EACCES:
return "IAVF_AQ_RC_EACCES";
case IAVF_AQ_RC_EFAULT:
return "IAVF_AQ_RC_EFAULT";
case IAVF_AQ_RC_EBUSY:
return "IAVF_AQ_RC_EBUSY";
case IAVF_AQ_RC_EEXIST:
return "IAVF_AQ_RC_EEXIST";
case IAVF_AQ_RC_EINVAL:
return "IAVF_AQ_RC_EINVAL";
case IAVF_AQ_RC_ENOTTY:
return "IAVF_AQ_RC_ENOTTY";
case IAVF_AQ_RC_ENOSPC:
return "IAVF_AQ_RC_ENOSPC";
case IAVF_AQ_RC_ENOSYS:
return "IAVF_AQ_RC_ENOSYS";
case IAVF_AQ_RC_ERANGE:
return "IAVF_AQ_RC_ERANGE";
case IAVF_AQ_RC_EFLUSHED:
return "IAVF_AQ_RC_EFLUSHED";
case IAVF_AQ_RC_BAD_ADDR:
return "IAVF_AQ_RC_BAD_ADDR";
case IAVF_AQ_RC_EMODE:
return "IAVF_AQ_RC_EMODE";
case IAVF_AQ_RC_EFBIG:
return "IAVF_AQ_RC_EFBIG";
}
snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
return hw->err_str;
}
/**
* iavf_stat_str - convert status err code to a string
* @hw: pointer to the HW structure
@ -228,7 +168,7 @@ const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status stat_err)
void iavf_debug_aq(struct iavf_hw *hw, enum iavf_debug_mask mask, void *desc,
void *buffer, u16 buf_len)
{
struct iavf_aq_desc *aq_desc = (struct iavf_aq_desc *)desc;
struct libie_aq_desc *aq_desc = (struct libie_aq_desc *)desc;
u8 *buf = (u8 *)buffer;
if ((!(mask & hw->debug_mask)) || !desc)
@ -244,11 +184,11 @@ void iavf_debug_aq(struct iavf_hw *hw, enum iavf_debug_mask mask, void *desc,
le32_to_cpu(aq_desc->cookie_high),
le32_to_cpu(aq_desc->cookie_low));
iavf_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
le32_to_cpu(aq_desc->params.internal.param0),
le32_to_cpu(aq_desc->params.internal.param1));
le32_to_cpu(aq_desc->params.generic.param0),
le32_to_cpu(aq_desc->params.generic.param1));
iavf_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
le32_to_cpu(aq_desc->params.external.addr_high),
le32_to_cpu(aq_desc->params.external.addr_low));
le32_to_cpu(aq_desc->params.generic.addr_high),
le32_to_cpu(aq_desc->params.generic.addr_low));
if (buffer && aq_desc->datalen) {
u16 len = le16_to_cpu(aq_desc->datalen);
@ -297,11 +237,11 @@ bool iavf_check_asq_alive(struct iavf_hw *hw)
**/
enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw, bool unloading)
{
struct iavf_aq_desc desc;
struct iavf_aqc_queue_shutdown *cmd =
(struct iavf_aqc_queue_shutdown *)&desc.params.raw;
struct iavf_aqc_queue_shutdown *cmd;
struct libie_aq_desc desc;
enum iavf_status status;
cmd = libie_aq_raw(&desc);
iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_queue_shutdown);
if (unloading)
@ -327,12 +267,13 @@ static enum iavf_status iavf_aq_get_set_rss_lut(struct iavf_hw *hw,
u8 *lut, u16 lut_size,
bool set)
{
struct iavf_aqc_get_set_rss_lut *cmd_resp;
struct libie_aq_desc desc;
enum iavf_status status;
struct iavf_aq_desc desc;
struct iavf_aqc_get_set_rss_lut *cmd_resp =
(struct iavf_aqc_get_set_rss_lut *)&desc.params.raw;
u16 flags;
cmd_resp = libie_aq_raw(&desc);
if (set)
iavf_fill_default_direct_cmd_desc(&desc,
iavf_aqc_opc_set_rss_lut);
@ -341,8 +282,8 @@ static enum iavf_status iavf_aq_get_set_rss_lut(struct iavf_hw *hw,
iavf_aqc_opc_get_rss_lut);
/* Indirect command */
desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_BUF);
desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_RD);
desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF);
desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD);
vsi_id = FIELD_PREP(IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) |
FIELD_PREP(IAVF_AQC_SET_RSS_LUT_VSI_VALID, 1);
@ -392,11 +333,12 @@ iavf_status iavf_aq_get_set_rss_key(struct iavf_hw *hw, u16 vsi_id,
struct iavf_aqc_get_set_rss_key_data *key,
bool set)
{
enum iavf_status status;
struct iavf_aq_desc desc;
struct iavf_aqc_get_set_rss_key *cmd_resp =
(struct iavf_aqc_get_set_rss_key *)&desc.params.raw;
u16 key_size = sizeof(struct iavf_aqc_get_set_rss_key_data);
struct iavf_aqc_get_set_rss_key *cmd_resp;
struct libie_aq_desc desc;
enum iavf_status status;
cmd_resp = libie_aq_raw(&desc);
if (set)
iavf_fill_default_direct_cmd_desc(&desc,
@ -406,8 +348,8 @@ iavf_status iavf_aq_get_set_rss_key(struct iavf_hw *hw, u16 vsi_id,
iavf_aqc_opc_get_rss_key);
/* Indirect command */
desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_BUF);
desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_RD);
desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF);
desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD);
vsi_id = FIELD_PREP(IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) |
FIELD_PREP(IAVF_AQC_SET_RSS_KEY_VSI_VALID, 1);
@ -452,18 +394,18 @@ enum iavf_status iavf_aq_send_msg_to_pf(struct iavf_hw *hw,
struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_asq_cmd_details details;
struct iavf_aq_desc desc;
struct libie_aq_desc desc;
enum iavf_status status;
iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_send_msg_to_pf);
desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_SI);
desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_SI);
desc.cookie_high = cpu_to_le32(v_opcode);
desc.cookie_low = cpu_to_le32(v_retval);
if (msglen) {
desc.flags |= cpu_to_le16((u16)(IAVF_AQ_FLAG_BUF
| IAVF_AQ_FLAG_RD));
desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF
| LIBIE_AQ_FLAG_RD));
if (msglen > IAVF_AQ_LARGE_BUF)
desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_LB);
desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB);
desc.datalen = cpu_to_le16(msglen);
}
if (!cmd_details) {

5
drivers/net/ethernet/intel/iavf/iavf_main.c
View File

@ -50,6 +50,7 @@ MODULE_ALIAS("i40evf");
MODULE_DESCRIPTION("Intel(R) Ethernet Adaptive Virtual Function Network Driver");
MODULE_IMPORT_NS("LIBETH");
MODULE_IMPORT_NS("LIBIE");
MODULE_IMPORT_NS("LIBIE_ADMINQ");
MODULE_LICENSE("GPL v2");
static const struct net_device_ops iavf_netdev_ops;
@ -1694,7 +1695,7 @@ static int iavf_config_rss_aq(struct iavf_adapter *adapter)
if (status) {
dev_err(&adapter->pdev->dev, "Cannot set RSS key, err %s aq_err %s\n",
iavf_stat_str(hw, status),
iavf_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
return iavf_status_to_errno(status);
}
@ -1704,7 +1705,7 @@ static int iavf_config_rss_aq(struct iavf_adapter *adapter)
if (status) {
dev_err(&adapter->pdev->dev, "Cannot set RSS lut, err %s aq_err %s\n",
iavf_stat_str(hw, status),
iavf_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
return iavf_status_to_errno(status);
}

3
drivers/net/ethernet/intel/iavf/iavf_prototype.h
View File

@ -22,7 +22,7 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
struct iavf_arq_event_info *e,
u16 *events_pending);
enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
struct iavf_aq_desc *desc,
struct libie_aq_desc *desc,
void *buff, /* can be NULL */
u16 buff_size,
struct iavf_asq_cmd_details *cmd_details);
@ -34,7 +34,6 @@ void iavf_debug_aq(struct iavf_hw *hw, enum iavf_debug_mask mask,
bool iavf_check_asq_alive(struct iavf_hw *hw);
enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw, bool unloading);
const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err);
const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status stat_err);
enum iavf_status iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 seid,

2
drivers/net/ethernet/intel/iavf/iavf_type.h
View File

@ -19,7 +19,7 @@
/* forward declaration */
struct iavf_hw;
typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *);
typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct libie_aq_desc *);
/* Data type manipulation macros. */

2
drivers/net/ethernet/intel/iavf/iavf_virtchnl.c
View File

@ -29,7 +29,7 @@ static int iavf_send_pf_msg(struct iavf_adapter *adapter,
if (status)
dev_dbg(&adapter->pdev->dev, "Unable to send opcode %d to PF, status %s, aq_err %s\n",
op, iavf_stat_str(hw, status),
iavf_aq_str(hw, hw->aq.asq_last_status));
libie_aq_str(hw->aq.asq_last_status));
return iavf_status_to_errno(status);
}

10
drivers/net/ethernet/intel/ice/devlink/devlink.c
View File

@ -293,7 +293,7 @@ static int ice_devlink_info_get(struct devlink *devlink,
err = ice_discover_dev_caps(hw, &ctx->dev_caps);
if (err) {
dev_dbg(dev, "Failed to discover device capabilities, status %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
NL_SET_ERR_MSG_MOD(extack, "Unable to discover device capabilities");
goto out_free_ctx;
}
@ -302,7 +302,7 @@ static int ice_devlink_info_get(struct devlink *devlink,
err = ice_get_inactive_orom_ver(hw, &ctx->pending_orom);
if (err) {
dev_dbg(dev, "Unable to read inactive Option ROM version data, status %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
/* disable display of pending Option ROM */
ctx->dev_caps.common_cap.nvm_update_pending_orom = false;
@ -313,7 +313,7 @@ static int ice_devlink_info_get(struct devlink *devlink,
err = ice_get_inactive_nvm_ver(hw, &ctx->pending_nvm);
if (err) {
dev_dbg(dev, "Unable to read inactive NVM version data, status %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
/* disable display of pending Option ROM */
ctx->dev_caps.common_cap.nvm_update_pending_nvm = false;
@ -324,7 +324,7 @@ static int ice_devlink_info_get(struct devlink *devlink,
err = ice_get_inactive_netlist_ver(hw, &ctx->pending_netlist);
if (err) {
dev_dbg(dev, "Unable to read inactive Netlist version data, status %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
/* disable display of pending Option ROM */
ctx->dev_caps.common_cap.nvm_update_pending_netlist = false;
@ -440,7 +440,7 @@ ice_devlink_reload_empr_start(struct ice_pf *pf,
err = ice_aq_nvm_update_empr(hw);
if (err) {
dev_err(dev, "Failed to trigger EMP device reset to reload firmware, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
NL_SET_ERR_MSG_MOD(extack, "Failed to trigger EMP device reset to reload firmware");
return err;
}

6
drivers/net/ethernet/intel/ice/devlink/health.c
View File

@ -204,7 +204,7 @@ static void ice_config_health_events(struct ice_pf *pf, bool enable)
if (ret)
dev_err(ice_pf_to_dev(pf), "Failed to %s firmware health events, err %d aq_err %s\n",
str_enable_disable(enable), ret,
ice_aq_str(pf->hw.adminq.sq_last_status));
libie_aq_str(pf->hw.adminq.sq_last_status));
}
/**
@ -217,10 +217,12 @@ static void ice_config_health_events(struct ice_pf *pf, bool enable)
void ice_process_health_status_event(struct ice_pf *pf, struct ice_rq_event_info *event)
{
const struct ice_aqc_health_status_elem *health_info;
const struct ice_aqc_get_health_status *cmd;
u16 count;
health_info = (struct ice_aqc_health_status_elem *)event->msg_buf;
count = le16_to_cpu(event->desc.params.get_health_status.health_status_count);
cmd = libie_aq_raw(&event->desc);
count = le16_to_cpu(cmd->health_status_count);
if (count > (event->buf_len / sizeof(*health_info))) {
dev_err(ice_pf_to_dev(pf), "Received a health status event with invalid element count\n");

1
drivers/net/ethernet/intel/ice/ice.h
View File

@ -960,7 +960,6 @@ int ice_plug_aux_dev(struct ice_pf *pf);
void ice_unplug_aux_dev(struct ice_pf *pf);
int ice_init_rdma(struct ice_pf *pf);
void ice_deinit_rdma(struct ice_pf *pf);
const char *ice_aq_str(enum ice_aq_err aq_err);
bool ice_is_wol_supported(struct ice_hw *hw);
void ice_fdir_del_all_fltrs(struct ice_vsi *vsi);
int

270
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
View File

@ -4,6 +4,8 @@
#ifndef _ICE_ADMINQ_CMD_H_
#define _ICE_ADMINQ_CMD_H_
#include <linux/net/intel/libie/adminq.h>
/* This header file defines the Admin Queue commands, error codes and
* descriptor format. It is shared between Firmware and Software.
*/
@ -31,38 +33,6 @@ typedef struct __packed { u8 buf[ICE_TXQ_CTX_SZ]; } ice_txq_ctx_buf_t;
typedef struct __packed { u8 buf[ICE_TXQ_CTX_FULL_SZ]; } ice_txq_ctx_buf_full_t;
struct ice_aqc_generic {
__le32 param0;
__le32 param1;
__le32 addr_high;
__le32 addr_low;
};
/* Get version (direct 0x0001) */
struct ice_aqc_get_ver {
__le32 rom_ver;
__le32 fw_build;
u8 fw_branch;
u8 fw_major;
u8 fw_minor;
u8 fw_patch;
u8 api_branch;
u8 api_major;
u8 api_minor;
u8 api_patch;
};
/* Send driver version (indirect 0x0002) */
struct ice_aqc_driver_ver {
u8 major_ver;
u8 minor_ver;
u8 build_ver;
u8 subbuild_ver;
u8 reserved[4];
__le32 addr_high;
__le32 addr_low;
};
/* Queue Shutdown (direct 0x0003) */
struct ice_aqc_q_shutdown {
u8 driver_unloading;
@ -70,94 +40,6 @@ struct ice_aqc_q_shutdown {
u8 reserved[15];
};
/* Request resource ownership (direct 0x0008)
* Release resource ownership (direct 0x0009)
*/
struct ice_aqc_req_res {
__le16 res_id;
#define ICE_AQC_RES_ID_NVM 1
#define ICE_AQC_RES_ID_SDP 2
#define ICE_AQC_RES_ID_CHNG_LOCK 3
#define ICE_AQC_RES_ID_GLBL_LOCK 4
__le16 access_type;
#define ICE_AQC_RES_ACCESS_READ 1
#define ICE_AQC_RES_ACCESS_WRITE 2
/* Upon successful completion, FW writes this value and driver is
* expected to release resource before timeout. This value is provided
* in milliseconds.
*/
__le32 timeout;
#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
/* For SDP: pin ID of the SDP */
__le32 res_number;
/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
__le16 status;
#define ICE_AQ_RES_GLBL_SUCCESS 0
#define ICE_AQ_RES_GLBL_IN_PROG 1
#define ICE_AQ_RES_GLBL_DONE 2
u8 reserved[2];
};
/* Get function capabilities (indirect 0x000A)
* Get device capabilities (indirect 0x000B)
*/
struct ice_aqc_list_caps {
u8 cmd_flags;
u8 pf_index;
u8 reserved[2];
__le32 count;
__le32 addr_high;
__le32 addr_low;
};
/* Device/Function buffer entry, repeated per reported capability */
struct ice_aqc_list_caps_elem {
__le16 cap;
#define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
#define ICE_AQC_CAPS_SRIOV 0x0012
#define ICE_AQC_CAPS_VF 0x0013
#define ICE_AQC_CAPS_VSI 0x0017
#define ICE_AQC_CAPS_DCB 0x0018
#define ICE_AQC_CAPS_RSS 0x0040
#define ICE_AQC_CAPS_RXQS 0x0041
#define ICE_AQC_CAPS_TXQS 0x0042
#define ICE_AQC_CAPS_MSIX 0x0043
#define ICE_AQC_CAPS_FD 0x0045
#define ICE_AQC_CAPS_1588 0x0046
#define ICE_AQC_CAPS_MAX_MTU 0x0047
#define ICE_AQC_CAPS_NVM_VER 0x0048
#define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049
#define ICE_AQC_CAPS_OROM_VER 0x004A
#define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B
#define ICE_AQC_CAPS_NET_VER 0x004C
#define ICE_AQC_CAPS_PENDING_NET_VER 0x004D
#define ICE_AQC_CAPS_RDMA 0x0051
#define ICE_AQC_CAPS_SENSOR_READING 0x0067
#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
#define ICE_AQC_CAPS_NVM_MGMT 0x0080
#define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085
#define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087
#define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092
#define ICE_AQC_BIT_ROCEV2_LAG 0x01
#define ICE_AQC_BIT_SRIOV_LAG 0x02
u8 major_ver;
u8 minor_ver;
/* Number of resources described by this capability */
__le32 number;
/* Only meaningful for some types of resources */
__le32 logical_id;
/* Only meaningful for some types of resources */
__le32 phys_id;
__le64 rsvd1;
__le64 rsvd2;
};
/* Manage MAC address, read command - indirect (0x0107)
* This struct is also used for the response
*/
@ -2672,154 +2554,6 @@ struct ice_aqc_fw_log_cfg_resp {
u8 rsvd0;
};
/**
* struct ice_aq_desc - Admin Queue (AQ) descriptor
* @flags: ICE_AQ_FLAG_* flags
* @opcode: AQ command opcode
* @datalen: length in bytes of indirect/external data buffer
* @retval: return value from firmware
* @cookie_high: opaque data high-half
* @cookie_low: opaque data low-half
* @params: command-specific parameters
*
* Descriptor format for commands the driver posts on the Admin Transmit Queue
* (ATQ). The firmware writes back onto the command descriptor and returns
* the result of the command. Asynchronous events that are not an immediate
* result of the command are written to the Admin Receive Queue (ARQ) using
* the same descriptor format. Descriptors are in little-endian notation with
* 32-bit words.
*/
struct ice_aq_desc {
__le16 flags;
__le16 opcode;
__le16 datalen;
__le16 retval;
__le32 cookie_high;
__le32 cookie_low;
union {
u8 raw[16];
struct ice_aqc_generic generic;
struct ice_aqc_get_ver get_ver;
struct ice_aqc_driver_ver driver_ver;
struct ice_aqc_q_shutdown q_shutdown;
struct ice_aqc_req_res res_owner;
struct ice_aqc_manage_mac_read mac_read;
struct ice_aqc_manage_mac_write mac_write;
struct ice_aqc_clear_pxe clear_pxe;
struct ice_aqc_list_caps get_cap;
struct ice_aqc_get_phy_caps get_phy;
struct ice_aqc_set_phy_cfg set_phy;
struct ice_aqc_restart_an restart_an;
struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out;
struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out;
struct ice_aqc_get_sensor_reading get_sensor_reading;
struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp;
struct ice_aqc_gpio read_write_gpio;
struct ice_aqc_sff_eeprom read_write_sff_param;
struct ice_aqc_set_port_id_led set_port_id_led;
struct ice_aqc_get_port_options get_port_options;
struct ice_aqc_set_port_option set_port_option;
struct ice_aqc_get_sw_cfg get_sw_conf;
struct ice_aqc_set_port_params set_port_params;
struct ice_aqc_sw_rules sw_rules;
struct ice_aqc_add_get_recipe add_get_recipe;
struct ice_aqc_recipe_to_profile recipe_to_profile;
struct ice_aqc_get_topo get_topo;
struct ice_aqc_sched_elem_cmd sched_elem_cmd;
struct ice_aqc_query_txsched_res query_sched_res;
struct ice_aqc_query_port_ets port_ets;
struct ice_aqc_rl_profile rl_profile;
struct ice_aqc_nvm nvm;
struct ice_aqc_nvm_checksum nvm_checksum;
struct ice_aqc_nvm_pkg_data pkg_data;
struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
struct ice_aqc_pf_vf_msg virt;
struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
struct ice_aqc_lldp_get_mib lldp_get_mib;
struct ice_aqc_lldp_set_mib_change lldp_set_event;
struct ice_aqc_lldp_stop lldp_stop;
struct ice_aqc_lldp_start lldp_start;
struct ice_aqc_lldp_set_local_mib lldp_set_mib;
struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
struct ice_aqc_get_set_rss_lut get_set_rss_lut;
struct ice_aqc_get_set_rss_key get_set_rss_key;
struct ice_aqc_neigh_dev_req neigh_dev;
struct ice_aqc_add_txqs add_txqs;
struct ice_aqc_dis_txqs dis_txqs;
struct ice_aqc_cfg_txqs cfg_txqs;
struct ice_aqc_add_rdma_qset add_rdma_qset;
struct ice_aqc_add_get_update_free_vsi vsi_cmd;
struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
struct ice_aqc_download_pkg download_pkg;
struct ice_aqc_get_cgu_input_measure get_cgu_input_measure;
struct ice_aqc_set_cgu_input_config set_cgu_input_config;
struct ice_aqc_get_cgu_input_config get_cgu_input_config;
struct ice_aqc_set_cgu_output_config set_cgu_output_config;
struct ice_aqc_get_cgu_output_config get_cgu_output_config;
struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status;
struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config;
struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio;
struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio;
struct ice_aqc_get_cgu_info get_cgu_info;
struct ice_aqc_driver_shared_params drv_shared_params;
struct ice_aqc_fw_log fw_log;
struct ice_aqc_set_mac_lb set_mac_lb;
struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
struct ice_aqc_set_mac_cfg set_mac_cfg;
struct ice_aqc_set_event_mask set_event_mask;
struct ice_aqc_get_link_status get_link_status;
struct ice_aqc_event_lan_overflow lan_overflow;
struct ice_aqc_get_link_topo get_link_topo;
struct ice_aqc_set_health_status_cfg set_health_status_cfg;
struct ice_aqc_get_health_status get_health_status;
struct ice_aqc_dnl_call_command dnl_call;
struct ice_aqc_i2c read_write_i2c;
struct ice_aqc_read_i2c_resp read_i2c_resp;
struct ice_aqc_get_set_tx_topo get_set_tx_topo;
} params;
};
/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
#define ICE_AQ_LG_BUF 512
#define ICE_AQ_FLAG_DD_S 0
#define ICE_AQ_FLAG_CMP_S 1
#define ICE_AQ_FLAG_ERR_S 2
#define ICE_AQ_FLAG_LB_S 9
#define ICE_AQ_FLAG_RD_S 10
#define ICE_AQ_FLAG_BUF_S 12
#define ICE_AQ_FLAG_SI_S 13
#define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
#define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
#define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
#define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
#define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
#define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
#define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
/* error codes */
enum ice_aq_err {
ICE_AQ_RC_OK = 0, /* Success */
ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
ICE_AQ_RC_ENOENT = 2, /* No such element */
ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
ICE_AQ_RC_EAGAIN = 8, /* Try again */
ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
ICE_AQ_RC_EEXIST = 13, /* Object already exists */
ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
};
/* Admin Queue command opcodes */
enum ice_adminq_opc {
/* AQ commands */

384
drivers/net/ethernet/intel/ice/ice_common.c
View File

File diff suppressed because it is too large Load Diff

6
drivers/net/ethernet/intel/ice/ice_common.h
View File

@ -109,7 +109,7 @@ bool ice_is_sbq_supported(struct ice_hw *hw);
struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw);
int
ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
struct ice_aq_desc *desc, void *buf, u16 buf_size,
struct libie_aq_desc *desc, void *buf, u16 buf_size,
struct ice_sq_cd *cd);
void ice_clear_pxe_mode(struct ice_hw *hw);
int ice_get_caps(struct ice_hw *hw);
@ -138,14 +138,14 @@ ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
void ice_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode);
void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf);
extern struct mutex ice_global_cfg_lock_sw;
int
ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc,
void *buf, u16 buf_size, struct ice_sq_cd *cd);
int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);

53
drivers/net/ethernet/intel/ice/ice_controlq.c
View File

@ -90,7 +90,7 @@ bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq)
static int
ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
{
size_t size = cq->num_sq_entries * sizeof(struct ice_aq_desc);
size_t size = cq->num_sq_entries * sizeof(struct libie_aq_desc);
cq->sq.desc_buf.va = dmam_alloc_coherent(ice_hw_to_dev(hw), size,
&cq->sq.desc_buf.pa,
@ -110,7 +110,7 @@ ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
static int
ice_alloc_ctrlq_rq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
{
size_t size = cq->num_rq_entries * sizeof(struct ice_aq_desc);
size_t size = cq->num_rq_entries * sizeof(struct libie_aq_desc);
cq->rq.desc_buf.va = dmam_alloc_coherent(ice_hw_to_dev(hw), size,
&cq->rq.desc_buf.pa,
@ -159,7 +159,7 @@ ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
/* allocate the mapped buffers */
for (i = 0; i < cq->num_rq_entries; i++) {
struct ice_aq_desc *desc;
struct libie_aq_desc *desc;
struct ice_dma_mem *bi;
bi = &cq->rq.r.rq_bi[i];
@ -173,9 +173,9 @@ ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
/* now configure the descriptors for use */
desc = ICE_CTL_Q_DESC(cq->rq, i);
desc->flags = cpu_to_le16(ICE_AQ_FLAG_BUF);
if (cq->rq_buf_size > ICE_AQ_LG_BUF)
desc->flags |= cpu_to_le16(ICE_AQ_FLAG_LB);
desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF);
if (cq->rq_buf_size > LIBIE_AQ_LG_BUF)
desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB);
desc->opcode = 0;
/* This is in accordance with control queue design, there is no
* register for buffer size configuration
@ -858,7 +858,7 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
{
struct ice_ctl_q_ring *sq = &cq->sq;
u16 ntc = sq->next_to_clean;
struct ice_aq_desc *desc;
struct libie_aq_desc *desc;
desc = ICE_CTL_Q_DESC(*sq, ntc);
@ -912,7 +912,7 @@ static const char *ice_ctl_q_str(enum ice_ctl_q qtype)
static void ice_debug_cq(struct ice_hw *hw, struct ice_ctl_q_info *cq,
void *desc, void *buf, u16 buf_len, bool response)
{
struct ice_aq_desc *cq_desc = desc;
struct libie_aq_desc *cq_desc = desc;
u16 datalen, flags;
if (!IS_ENABLED(CONFIG_DYNAMIC_DEBUG) &&
@ -939,7 +939,8 @@ static void ice_debug_cq(struct ice_hw *hw, struct ice_ctl_q_info *cq,
* by the DD and/or CMP flag set or a command with the RD flag set.
*/
if (buf && cq_desc->datalen &&
(flags & (ICE_AQ_FLAG_DD | ICE_AQ_FLAG_CMP | ICE_AQ_FLAG_RD))) {
(flags & (LIBIE_AQ_FLAG_DD | LIBIE_AQ_FLAG_CMP |
LIBIE_AQ_FLAG_RD))) {
char prefix[] = KBUILD_MODNAME " 0x12341234 0x12341234 ";
sprintf(prefix, KBUILD_MODNAME " 0x%08X 0x%08X ",
@ -992,11 +993,11 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
*/
int
ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
struct ice_aq_desc *desc, void *buf, u16 buf_size,
struct libie_aq_desc *desc, void *buf, u16 buf_size,
struct ice_sq_cd *cd)
{
struct ice_dma_mem *dma_buf = NULL;
struct ice_aq_desc *desc_on_ring;
struct libie_aq_desc *desc_on_ring;
bool cmd_completed = false;
int status = 0;
u16 retval = 0;
@ -1007,7 +1008,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
return -EBUSY;
mutex_lock(&cq->sq_lock);
cq->sq_last_status = ICE_AQ_RC_OK;
cq->sq_last_status = LIBIE_AQ_RC_OK;
if (!cq->sq.count) {
ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send queue not initialized.\n");
@ -1028,9 +1029,9 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
goto sq_send_command_error;
}
desc->flags |= cpu_to_le16(ICE_AQ_FLAG_BUF);
if (buf_size > ICE_AQ_LG_BUF)
desc->flags |= cpu_to_le16(ICE_AQ_FLAG_LB);
desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF);
if (buf_size > LIBIE_AQ_LG_BUF)
desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB);
}
val = rd32(hw, cq->sq.head);
@ -1112,9 +1113,9 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
retval &= 0xff;
}
cmd_completed = true;
if (!status && retval != ICE_AQ_RC_OK)
if (!status && retval != LIBIE_AQ_RC_OK)
status = -EIO;
cq->sq_last_status = (enum ice_aq_err)retval;
cq->sq_last_status = (enum libie_aq_err)retval;
}
ice_debug(hw, ICE_DBG_AQ_MSG, "ATQ: desc and buffer writeback:\n");
@ -1149,12 +1150,12 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
*
* Fill the desc with default values
*/
void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode)
void ice_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode)
{
/* zero out the desc */
memset(desc, 0, sizeof(*desc));
desc->opcode = cpu_to_le16(opcode);
desc->flags = cpu_to_le16(ICE_AQ_FLAG_SI);
desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI);
}
/**
@ -1172,9 +1173,9 @@ int
ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
struct ice_rq_event_info *e, u16 *pending)
{
enum libie_aq_err rq_last_status;
u16 ntc = cq->rq.next_to_clean;
enum ice_aq_err rq_last_status;
struct ice_aq_desc *desc;
struct libie_aq_desc *desc;
struct ice_dma_mem *bi;
int ret_code = 0;
u16 desc_idx;
@ -1207,9 +1208,9 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
desc = ICE_CTL_Q_DESC(cq->rq, ntc);
desc_idx = ntc;
rq_last_status = (enum ice_aq_err)le16_to_cpu(desc->retval);
rq_last_status = (enum libie_aq_err)le16_to_cpu(desc->retval);
flags = le16_to_cpu(desc->flags);
if (flags & ICE_AQ_FLAG_ERR) {
if (flags & LIBIE_AQ_FLAG_ERR) {
ret_code = -EIO;
ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive Queue Event 0x%04X received with error 0x%X\n",
le16_to_cpu(desc->opcode), rq_last_status);
@ -1230,9 +1231,9 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
bi = &cq->rq.r.rq_bi[ntc];
memset(desc, 0, sizeof(*desc));
desc->flags = cpu_to_le16(ICE_AQ_FLAG_BUF);
if (cq->rq_buf_size > ICE_AQ_LG_BUF)
desc->flags |= cpu_to_le16(ICE_AQ_FLAG_LB);
desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF);
if (cq->rq_buf_size > LIBIE_AQ_LG_BUF)
desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB);
desc->datalen = cpu_to_le16(bi->size);
desc->params.generic.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
desc->params.generic.addr_low = cpu_to_le32(lower_32_bits(bi->pa));

8
drivers/net/ethernet/intel/ice/ice_controlq.h
View File

@ -12,7 +12,7 @@
#define ICE_SBQ_MAX_BUF_LEN 512
#define ICE_CTL_Q_DESC(R, i) \
(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
(&(((struct libie_aq_desc *)((R).desc_buf.va))[i]))
#define ICE_CTL_Q_DESC_UNUSED(R) \
((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
@ -76,12 +76,12 @@ struct ice_ctl_q_ring {
/* sq transaction details */
struct ice_sq_cd {
struct ice_aq_desc *wb_desc;
struct libie_aq_desc *wb_desc;
};
/* rq event information */
struct ice_rq_event_info {
struct ice_aq_desc desc;
struct libie_aq_desc desc;
u16 msg_len;
u16 buf_len;
u8 *msg_buf;
@ -96,7 +96,7 @@ struct ice_ctl_q_info {
u16 num_sq_entries; /* send queue depth */
u16 rq_buf_size; /* receive queue buffer size */
u16 sq_buf_size; /* send queue buffer size */
enum ice_aq_err sq_last_status; /* last status on send queue */
enum libie_aq_err sq_last_status; /* last status on send queue */
struct mutex sq_lock; /* Send queue lock */
struct mutex rq_lock; /* Receive queue lock */
};

36
drivers/net/ethernet/intel/ice/ice_dcb.c
View File

@ -24,10 +24,10 @@ ice_aq_get_lldp_mib(struct ice_hw *hw, u8 bridge_type, u8 mib_type, void *buf,
struct ice_sq_cd *cd)
{
struct ice_aqc_lldp_get_mib *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
cmd = &desc.params.lldp_get_mib;
cmd = libie_aq_raw(&desc);
if (buf_size == 0 || !buf)
return -EINVAL;
@ -64,9 +64,9 @@ ice_aq_cfg_lldp_mib_change(struct ice_hw *hw, bool ena_update,
struct ice_sq_cd *cd)
{
struct ice_aqc_lldp_set_mib_change *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
cmd = &desc.params.lldp_set_event;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_mib_change);
@ -95,9 +95,9 @@ ice_aq_stop_lldp(struct ice_hw *hw, bool shutdown_lldp_agent, bool persist,
struct ice_sq_cd *cd)
{
struct ice_aqc_lldp_stop *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
cmd = &desc.params.lldp_stop;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_stop);
@ -121,9 +121,9 @@ ice_aq_stop_lldp(struct ice_hw *hw, bool shutdown_lldp_agent, bool persist,
int ice_aq_start_lldp(struct ice_hw *hw, bool persist, struct ice_sq_cd *cd)
{
struct ice_aqc_lldp_start *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
cmd = &desc.params.lldp_start;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_start);
@ -677,11 +677,11 @@ ice_aq_start_stop_dcbx(struct ice_hw *hw, bool start_dcbx_agent,
bool *dcbx_agent_status, struct ice_sq_cd *cd)
{
struct ice_aqc_lldp_stop_start_specific_agent *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
u16 opcode;
int status;
cmd = &desc.params.lldp_agent_ctrl;
cmd = libie_aq_raw(&desc);
opcode = ice_aqc_opc_lldp_stop_start_specific_agent;
@ -714,7 +714,7 @@ ice_aq_get_cee_dcb_cfg(struct ice_hw *hw,
struct ice_aqc_get_cee_dcb_cfg_resp *buff,
struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
struct libie_aq_desc desc;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cee_dcb_cfg);
@ -733,13 +733,13 @@ ice_aq_get_cee_dcb_cfg(struct ice_hw *hw,
int ice_aq_set_pfc_mode(struct ice_hw *hw, u8 pfc_mode, struct ice_sq_cd *cd)
{
struct ice_aqc_set_query_pfc_mode *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
if (pfc_mode > ICE_AQC_PFC_DSCP_BASED_PFC)
return -EINVAL;
cmd = &desc.params.set_query_pfc_mode;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_pfc_mode);
@ -914,7 +914,7 @@ static int ice_get_ieee_or_cee_dcb_cfg(struct ice_port_info *pi, u8 dcbx_mode)
ret = ice_aq_get_dcb_cfg(pi->hw, ICE_AQ_LLDP_MIB_REMOTE,
ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID, dcbx_cfg);
/* Don't treat ENOENT as an error for Remote MIBs */
if (pi->hw->adminq.sq_last_status == ICE_AQ_RC_ENOENT)
if (pi->hw->adminq.sq_last_status == LIBIE_AQ_RC_ENOENT)
ret = 0;
out:
@ -941,7 +941,7 @@ int ice_get_dcb_cfg(struct ice_port_info *pi)
/* CEE mode */
ret = ice_get_ieee_or_cee_dcb_cfg(pi, ICE_DCBX_MODE_CEE);
ice_cee_to_dcb_cfg(&cee_cfg, pi);
} else if (pi->hw->adminq.sq_last_status == ICE_AQ_RC_ENOENT) {
} else if (pi->hw->adminq.sq_last_status == LIBIE_AQ_RC_ENOENT) {
/* CEE mode not enabled try querying IEEE data */
dcbx_cfg = &pi->qos_cfg.local_dcbx_cfg;
dcbx_cfg->dcbx_mode = ICE_DCBX_MODE_IEEE;
@ -965,7 +965,7 @@ void ice_get_dcb_cfg_from_mib_change(struct ice_port_info *pi,
struct ice_aqc_lldp_get_mib *mib;
u8 change_type, dcbx_mode;
mib = (struct ice_aqc_lldp_get_mib *)&event->desc.params.raw;
mib = libie_aq_raw(&event->desc);
change_type = FIELD_GET(ICE_AQ_LLDP_MIB_TYPE_M, mib->type);
if (change_type == ICE_AQ_LLDP_MIB_REMOTE)
@ -1537,12 +1537,12 @@ ice_aq_query_port_ets(struct ice_port_info *pi,
struct ice_sq_cd *cd)
{
struct ice_aqc_query_port_ets *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
if (!pi)
return -EINVAL;
cmd = &desc.params.port_ets;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_port_ets);
cmd->port_teid = pi->root->info.node_teid;

2
drivers/net/ethernet/intel/ice/ice_dcb_lib.c
View File

@ -1020,7 +1020,7 @@ ice_dcb_process_lldp_set_mib_change(struct ice_pf *pf,
}
pi = pf->hw.port_info;
mib = (struct ice_aqc_lldp_get_mib *)&event->desc.params.raw;
mib = libie_aq_raw(&event->desc);
/* Ignore if event is not for Nearest Bridge */
mib_type = FIELD_GET(ICE_AQ_LLDP_BRID_TYPE_M, mib->type);

47
drivers/net/ethernet/intel/ice/ice_ddp.c
View File

@ -1101,16 +1101,16 @@ struct ice_buf *ice_pkg_buf(struct ice_buf_build *bld)
return &bld->buf;
}
static enum ice_ddp_state ice_map_aq_err_to_ddp_state(enum ice_aq_err aq_err)
static enum ice_ddp_state ice_map_aq_err_to_ddp_state(enum libie_aq_err aq_err)
{
switch (aq_err) {
case ICE_AQ_RC_ENOSEC:
case ICE_AQ_RC_EBADSIG:
case LIBIE_AQ_RC_ENOSEC:
case LIBIE_AQ_RC_EBADSIG:
return ICE_DDP_PKG_FILE_SIGNATURE_INVALID;
case ICE_AQ_RC_ESVN:
case LIBIE_AQ_RC_ESVN:
return ICE_DDP_PKG_FILE_REVISION_TOO_LOW;
case ICE_AQ_RC_EBADMAN:
case ICE_AQ_RC_EBADBUF:
case LIBIE_AQ_RC_EBADMAN:
case LIBIE_AQ_RC_EBADBUF:
return ICE_DDP_PKG_LOAD_ERROR;
default:
return ICE_DDP_PKG_ERR;
@ -1180,7 +1180,7 @@ ice_aq_download_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf,
u32 *error_info, struct ice_sq_cd *cd)
{
struct ice_aqc_download_pkg *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
if (error_offset)
@ -1188,9 +1188,9 @@ ice_aq_download_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf,
if (error_info)
*error_info = 0;
cmd = &desc.params.download_pkg;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_download_pkg);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
if (last_buf)
cmd->flags |= ICE_AQC_DOWNLOAD_PKG_LAST_BUF;
@ -1259,7 +1259,7 @@ static enum ice_ddp_state ice_ddp_send_hunk(struct ice_ddp_send_ctx *ctx,
struct ice_buf_hdr *prev_hunk = ctx->hdr;
struct ice_hw *hw = ctx->hw;
bool prev_was_last = !hunk;
enum ice_aq_err aq_err;
enum libie_aq_err aq_err;
u32 offset, info;
int attempt, err;
@ -1278,7 +1278,8 @@ static enum ice_ddp_state ice_ddp_send_hunk(struct ice_ddp_send_ctx *ctx,
prev_was_last, &offset, &info, NULL);
aq_err = hw->adminq.sq_last_status;
if (aq_err != ICE_AQ_RC_ENOSEC && aq_err != ICE_AQ_RC_EBADSIG)
if (aq_err != LIBIE_AQ_RC_ENOSEC &&
aq_err != LIBIE_AQ_RC_EBADSIG)
break;
}
@ -1537,7 +1538,7 @@ ice_post_dwnld_pkg_actions(struct ice_hw *hw)
static enum ice_ddp_state
ice_download_pkg_with_sig_seg(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr)
{
enum ice_aq_err aq_err = hw->adminq.sq_last_status;
enum libie_aq_err aq_err = hw->adminq.sq_last_status;
enum ice_ddp_state state = ICE_DDP_PKG_ERR;
struct ice_ddp_send_ctx ctx = { .hw = hw };
int status;
@ -1687,7 +1688,7 @@ static int ice_aq_get_pkg_info_list(struct ice_hw *hw,
struct ice_aqc_get_pkg_info_resp *pkg_info,
u16 buf_size, struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
struct libie_aq_desc desc;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_pkg_info_list);
@ -1711,7 +1712,7 @@ static int ice_aq_update_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf,
u32 *error_info, struct ice_sq_cd *cd)
{
struct ice_aqc_download_pkg *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
if (error_offset)
@ -1719,9 +1720,9 @@ static int ice_aq_update_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf,
if (error_info)
*error_info = 0;
cmd = &desc.params.download_pkg;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_update_pkg);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
if (last_buf)
cmd->flags |= ICE_AQC_DOWNLOAD_PKG_LAST_BUF;
@ -1753,10 +1754,10 @@ static int ice_aq_update_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf,
int ice_aq_upload_section(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf,
u16 buf_size, struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
struct libie_aq_desc desc;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_upload_section);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
return ice_aq_send_cmd(hw, &desc, pkg_buf, buf_size, cd);
}
@ -2335,10 +2336,10 @@ ice_get_set_tx_topo(struct ice_hw *hw, u8 *buf, u16 buf_size,
struct ice_sq_cd *cd, u8 *flags, bool set)
{
struct ice_aqc_get_set_tx_topo *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
cmd = &desc.params.get_set_tx_topo;
cmd = libie_aq_raw(&desc);
if (set) {
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_tx_topo);
cmd->set_flags = ICE_AQC_TX_TOPO_FLAGS_ISSUED;
@ -2347,14 +2348,14 @@ ice_get_set_tx_topo(struct ice_hw *hw, u8 *buf, u16 buf_size,
cmd->set_flags |= ICE_AQC_TX_TOPO_FLAGS_SRC_RAM |
ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW;
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
} else {
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_tx_topo);
cmd->get_flags = ICE_AQC_TX_TOPO_GET_RAM;
if (hw->mac_type == ICE_MAC_E810 ||
hw->mac_type == ICE_MAC_GENERIC)
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
}
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
@ -2362,7 +2363,7 @@ ice_get_set_tx_topo(struct ice_hw *hw, u8 *buf, u16 buf_size,
return status;
/* read the return flag values (first byte) for get operation */
if (!set && flags)
*flags = desc.params.get_set_tx_topo.set_flags;
*flags = cmd->set_flags;
return 0;
}

26
drivers/net/ethernet/intel/ice/ice_dpll.c
View File

@ -170,7 +170,7 @@ ice_dpll_pin_freq_set(struct ice_pf *pf, struct ice_dpll_pin *pin,
NL_SET_ERR_MSG_FMT(extack,
"err:%d %s failed to set pin freq:%u on pin:%u",
ret,
ice_aq_str(pf->hw.adminq.sq_last_status),
libie_aq_str(pf->hw.adminq.sq_last_status),
freq, pin->idx);
return ret;
}
@ -477,7 +477,7 @@ ice_dpll_pin_enable(struct ice_hw *hw, struct ice_dpll_pin *pin,
if (ret)
NL_SET_ERR_MSG_FMT(extack,
"err:%d %s failed to enable %s pin:%u",
ret, ice_aq_str(hw->adminq.sq_last_status),
ret, libie_aq_str(hw->adminq.sq_last_status),
pin_type_name[pin_type], pin->idx);
return ret;
@ -522,7 +522,7 @@ ice_dpll_pin_disable(struct ice_hw *hw, struct ice_dpll_pin *pin,
if (ret)
NL_SET_ERR_MSG_FMT(extack,
"err:%d %s failed to disable %s pin:%u",
ret, ice_aq_str(hw->adminq.sq_last_status),
ret, libie_aq_str(hw->adminq.sq_last_status),
pin_type_name[pin_type], pin->idx);
return ret;
@ -701,13 +701,13 @@ ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
NL_SET_ERR_MSG_FMT(extack,
"err:%d %s failed to update %s pin:%u",
ret,
ice_aq_str(pf->hw.adminq.sq_last_status),
libie_aq_str(pf->hw.adminq.sq_last_status),
pin_type_name[pin_type], pin->idx);
else
dev_err_ratelimited(ice_pf_to_dev(pf),
"err:%d %s failed to update %s pin:%u\n",
ret,
ice_aq_str(pf->hw.adminq.sq_last_status),
libie_aq_str(pf->hw.adminq.sq_last_status),
pin_type_name[pin_type], pin->idx);
return ret;
}
@ -740,7 +740,7 @@ ice_dpll_hw_input_prio_set(struct ice_pf *pf, struct ice_dpll *dpll,
NL_SET_ERR_MSG_FMT(extack,
"err:%d %s failed to set pin prio:%u on pin:%u",
ret,
ice_aq_str(pf->hw.adminq.sq_last_status),
libie_aq_str(pf->hw.adminq.sq_last_status),
prio, pin->idx);
else
dpll->input_prio[pin->idx] = prio;
@ -1662,7 +1662,7 @@ ice_dpll_pin_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
NL_SET_ERR_MSG_FMT(extack,
"err:%d %s failed to set pin phase_adjust:%d for pin:%u on dpll:%u",
ret,
ice_aq_str(pf->hw.adminq.sq_last_status),
libie_aq_str(pf->hw.adminq.sq_last_status),
phase_adjust, p->idx, d->dpll_idx);
return ret;
@ -2313,7 +2313,7 @@ ice_dpll_rclk_state_on_pin_set(const struct dpll_pin *pin, void *pin_priv,
NL_SET_ERR_MSG_FMT(extack,
"err:%d %s failed to set pin state:%u for pin:%u on parent:%u",
ret,
ice_aq_str(pf->hw.adminq.sq_last_status),
libie_aq_str(pf->hw.adminq.sq_last_status),
state, p->idx, parent->idx);
unlock:
mutex_unlock(&pf->dplls.lock);
@ -2509,7 +2509,7 @@ static bool ice_dpll_is_pps_phase_monitor(struct ice_pf *pf)
int ret = ice_aq_get_cgu_input_pin_measure(&pf->hw, DPLL_TYPE_PPS, meas,
ARRAY_SIZE(meas));
if (ret && pf->hw.adminq.sq_last_status == ICE_AQ_RC_ESRCH)
if (ret && pf->hw.adminq.sq_last_status == LIBIE_AQ_RC_ESRCH)
return false;
return true;
@ -2562,13 +2562,13 @@ static int ice_dpll_pps_update_phase_offsets(struct ice_pf *pf,
*phase_offset_pins_updated = 0;
ret = ice_aq_get_cgu_input_pin_measure(&pf->hw, DPLL_TYPE_PPS, meas,
ARRAY_SIZE(meas));
if (ret && pf->hw.adminq.sq_last_status == ICE_AQ_RC_EAGAIN) {
if (ret && pf->hw.adminq.sq_last_status == LIBIE_AQ_RC_EAGAIN) {
return 0;
} else if (ret) {
dev_err(ice_pf_to_dev(pf),
"failed to get input pin measurements dpll=%d, ret=%d %s\n",
DPLL_TYPE_PPS, ret,
ice_aq_str(pf->hw.adminq.sq_last_status));
libie_aq_str(pf->hw.adminq.sq_last_status));
return ret;
}
for (i = 0; i < pf->dplls.num_inputs; i++) {
@ -2627,7 +2627,7 @@ ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init)
dev_err(ice_pf_to_dev(pf),
"update dpll=%d state failed, ret=%d %s\n",
d->dpll_idx, ret,
ice_aq_str(pf->hw.adminq.sq_last_status));
libie_aq_str(pf->hw.adminq.sq_last_status));
return ret;
}
if (init) {
@ -3678,7 +3678,7 @@ static int ice_dpll_init_info(struct ice_pf *pf, bool cgu)
if (ret) {
dev_err(ice_pf_to_dev(pf),
"err:%d %s failed to read cgu abilities\n",
ret, ice_aq_str(hw->adminq.sq_last_status));
ret, libie_aq_str(hw->adminq.sq_last_status));
return ret;
}

12
drivers/net/ethernet/intel/ice/ice_ethtool.c
View File

@ -879,7 +879,7 @@ ice_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom,
ret = ice_acquire_nvm(hw, ICE_RES_READ);
if (ret) {
dev_err(dev, "ice_acquire_nvm failed, err %d aq_err %s\n",
ret, ice_aq_str(hw->adminq.sq_last_status));
ret, libie_aq_str(hw->adminq.sq_last_status));
goto out;
}
@ -887,7 +887,7 @@ ice_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom,
false);
if (ret) {
dev_err(dev, "ice_read_flat_nvm failed, err %d aq_err %s\n",
ret, ice_aq_str(hw->adminq.sq_last_status));
ret, libie_aq_str(hw->adminq.sq_last_status));
goto release;
}
@ -3542,15 +3542,15 @@ ice_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
if (aq_failures & ICE_SET_FC_AQ_FAIL_GET) {
netdev_info(netdev, "Set fc failed on the get_phy_capabilities call with err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
err = -EAGAIN;
} else if (aq_failures & ICE_SET_FC_AQ_FAIL_SET) {
netdev_info(netdev, "Set fc failed on the set_phy_config call with err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
err = -EAGAIN;
} else if (aq_failures & ICE_SET_FC_AQ_FAIL_UPDATE) {
netdev_info(netdev, "Set fc failed on the get_link_info call with err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
err = -EAGAIN;
}
@ -3861,7 +3861,7 @@ static int ice_vsi_set_dflt_rss_lut(struct ice_vsi *vsi, int req_rss_size)
err = ice_set_rss_lut(vsi, lut, vsi->rss_table_size);
if (err)
dev_err(dev, "Cannot set RSS lut, err %d aq_err %s\n", err,
ice_aq_str(hw->adminq.sq_last_status));
libie_aq_str(hw->adminq.sq_last_status));
kfree(lut);
return err;

38
drivers/net/ethernet/intel/ice/ice_fw_update.c
View File

@ -68,7 +68,7 @@ ice_send_package_data(struct pldmfw *context, const u8 *data, u16 length)
if (status) {
dev_err(dev, "Failed to send record package data to firmware, err %d aq_err %s\n",
status, ice_aq_str(hw->adminq.sq_last_status));
status, libie_aq_str(hw->adminq.sq_last_status));
NL_SET_ERR_MSG_MOD(extack, "Failed to record package data to firmware");
return -EIO;
}
@ -257,7 +257,7 @@ ice_send_component_table(struct pldmfw *context, struct pldmfw_component *compon
if (status) {
dev_err(dev, "Failed to transfer component table to firmware, err %d aq_err %s\n",
status, ice_aq_str(hw->adminq.sq_last_status));
status, libie_aq_str(hw->adminq.sq_last_status));
NL_SET_ERR_MSG_MOD(extack, "Failed to transfer component table to firmware");
return -EIO;
}
@ -299,7 +299,8 @@ int ice_write_one_nvm_block(struct ice_pf *pf, u16 module, u32 offset,
struct device *dev = ice_pf_to_dev(pf);
struct ice_aq_task task = {};
struct ice_hw *hw = &pf->hw;
struct ice_aq_desc *desc;
struct libie_aq_desc *desc;
struct ice_aqc_nvm *cmd;
u32 completion_offset;
int err;
@ -313,7 +314,7 @@ int ice_write_one_nvm_block(struct ice_pf *pf, u16 module, u32 offset,
if (err) {
dev_err(dev, "Failed to flash module 0x%02x with block of size %u at offset %u, err %d aq_err %s\n",
module, block_size, offset, err,
ice_aq_str(hw->adminq.sq_last_status));
libie_aq_str(hw->adminq.sq_last_status));
NL_SET_ERR_MSG_MOD(extack, "Failed to program flash module");
return -EIO;
}
@ -333,11 +334,12 @@ int ice_write_one_nvm_block(struct ice_pf *pf, u16 module, u32 offset,
}
desc = &task.event.desc;
completion_module = le16_to_cpu(desc->params.nvm.module_typeid);
cmd = libie_aq_raw(desc);
completion_module = le16_to_cpu(cmd->module_typeid);
completion_retval = le16_to_cpu(desc->retval);
completion_offset = le16_to_cpu(desc->params.nvm.offset_low);
completion_offset |= desc->params.nvm.offset_high << 16;
completion_offset = le16_to_cpu(cmd->offset_low);
completion_offset |= cmd->offset_high << 16;
if (completion_module != module) {
dev_err(dev, "Unexpected module_typeid in write completion: got 0x%x, expected 0x%x\n",
@ -356,7 +358,7 @@ int ice_write_one_nvm_block(struct ice_pf *pf, u16 module, u32 offset,
if (completion_retval) {
dev_err(dev, "Firmware failed to flash module 0x%02x with block of size %u at offset %u, err %s\n",
module, block_size, offset,
ice_aq_str((enum ice_aq_err)completion_retval));
libie_aq_str((enum libie_aq_err)completion_retval));
NL_SET_ERR_MSG_MOD(extack, "Firmware failed to program flash module");
return -EIO;
}
@ -369,7 +371,7 @@ int ice_write_one_nvm_block(struct ice_pf *pf, u16 module, u32 offset,
*/
if (reset_level && last_cmd && module == ICE_SR_1ST_NVM_BANK_PTR) {
if (hw->dev_caps.common_cap.pcie_reset_avoidance) {
*reset_level = desc->params.nvm.cmd_flags &
*reset_level = cmd->cmd_flags &
ICE_AQC_NVM_RESET_LVL_M;
dev_dbg(dev, "Firmware reported required reset level as %u\n",
*reset_level);
@ -487,7 +489,8 @@ ice_erase_nvm_module(struct ice_pf *pf, u16 module, const char *component,
struct device *dev = ice_pf_to_dev(pf);
struct ice_aq_task task = {};
struct ice_hw *hw = &pf->hw;
struct ice_aq_desc *desc;
struct libie_aq_desc *desc;
struct ice_aqc_nvm *cmd;
struct devlink *devlink;
int err;
@ -503,7 +506,7 @@ ice_erase_nvm_module(struct ice_pf *pf, u16 module, const char *component,
if (err) {
dev_err(dev, "Failed to erase %s (module 0x%02x), err %d aq_err %s\n",
component, module, err,
ice_aq_str(hw->adminq.sq_last_status));
libie_aq_str(hw->adminq.sq_last_status));
NL_SET_ERR_MSG_MOD(extack, "Failed to erase flash module");
err = -EIO;
goto out_notify_devlink;
@ -518,7 +521,8 @@ ice_erase_nvm_module(struct ice_pf *pf, u16 module, const char *component,
}
desc = &task.event.desc;
completion_module = le16_to_cpu(desc->params.nvm.module_typeid);
cmd = libie_aq_raw(desc);
completion_module = le16_to_cpu(cmd->module_typeid);
completion_retval = le16_to_cpu(desc->retval);
if (completion_module != module) {
@ -532,7 +536,7 @@ ice_erase_nvm_module(struct ice_pf *pf, u16 module, const char *component,
if (completion_retval) {
dev_err(dev, "Firmware failed to erase %s (module 0x02%x), aq_err %s\n",
component, module,
ice_aq_str((enum ice_aq_err)completion_retval));
libie_aq_str((enum libie_aq_err)completion_retval));
NL_SET_ERR_MSG_MOD(extack, "Firmware failed to erase flash");
err = -EIO;
goto out_notify_devlink;
@ -579,7 +583,7 @@ ice_switch_flash_banks(struct ice_pf *pf, u8 activate_flags,
err = ice_nvm_write_activate(hw, activate_flags, &response_flags);
if (err) {
dev_err(dev, "Failed to switch active flash banks, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
NL_SET_ERR_MSG_MOD(extack, "Failed to switch active flash banks");
return -EIO;
}
@ -611,7 +615,7 @@ ice_switch_flash_banks(struct ice_pf *pf, u8 activate_flags,
completion_retval = le16_to_cpu(task.event.desc.retval);
if (completion_retval) {
dev_err(dev, "Firmware failed to switch active flash banks aq_err %s\n",
ice_aq_str((enum ice_aq_err)completion_retval));
libie_aq_str((enum libie_aq_err)completion_retval));
NL_SET_ERR_MSG_MOD(extack, "Firmware failed to switch active flash banks");
return -EIO;
}
@ -949,7 +953,7 @@ ice_cancel_pending_update(struct ice_pf *pf, const char *component,
err = ice_acquire_nvm(hw, ICE_RES_WRITE);
if (err) {
dev_err(dev, "Failed to acquire device flash lock, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
NL_SET_ERR_MSG_MOD(extack, "Failed to acquire device flash lock");
return err;
}
@ -1042,7 +1046,7 @@ int ice_devlink_flash_update(struct devlink *devlink,
err = ice_acquire_nvm(hw, ICE_RES_WRITE);
if (err) {
dev_err(dev, "Failed to acquire device flash lock, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
NL_SET_ERR_MSG_MOD(extack, "Failed to acquire device flash lock");
return err;
}

16
drivers/net/ethernet/intel/ice/ice_fwlog.c
View File

@ -240,7 +240,7 @@ ice_aq_fwlog_set(struct ice_hw *hw, struct ice_fwlog_module_entry *entries,
{
struct ice_aqc_fw_log_cfg_resp *fw_modules;
struct ice_aqc_fw_log *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
int i;
@ -255,9 +255,9 @@ ice_aq_fwlog_set(struct ice_hw *hw, struct ice_fwlog_module_entry *entries,
}
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logs_config);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
cmd = &desc.params.fw_log;
cmd = libie_aq_raw(&desc);
cmd->cmd_flags = ICE_AQC_FW_LOG_CONF_SET_VALID;
cmd->ops.cfg.log_resolution = cpu_to_le16(log_resolution);
@ -309,7 +309,7 @@ static int ice_aq_fwlog_get(struct ice_hw *hw, struct ice_fwlog_cfg *cfg)
{
struct ice_aqc_fw_log_cfg_resp *fw_modules;
struct ice_aqc_fw_log *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
u16 module_id_cnt;
int status;
void *buf;
@ -322,7 +322,7 @@ static int ice_aq_fwlog_get(struct ice_hw *hw, struct ice_fwlog_cfg *cfg)
return -ENOMEM;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logs_query);
cmd = &desc.params.fw_log;
cmd = libie_aq_raw(&desc);
cmd->cmd_flags = ICE_AQC_FW_LOG_AQ_QUERY;
@ -384,12 +384,14 @@ int ice_fwlog_get(struct ice_hw *hw, struct ice_fwlog_cfg *cfg)
*/
static int ice_aq_fwlog_register(struct ice_hw *hw, bool reg)
{
struct ice_aq_desc desc;
struct ice_aqc_fw_log *cmd;
struct libie_aq_desc desc;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logs_register);
cmd = libie_aq_raw(&desc);
if (reg)
desc.params.fw_log.cmd_flags = ICE_AQC_FW_LOG_AQ_REGISTER;
cmd->cmd_flags = ICE_AQC_FW_LOG_AQ_REGISTER;
return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
}

4
drivers/net/ethernet/intel/ice/ice_lag.c
View File

@ -1144,7 +1144,7 @@ ice_lag_set_swid(u16 primary_swid, struct ice_lag *local_lag,
{
struct ice_aqc_alloc_free_res_elem *buf;
struct ice_aqc_set_port_params *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
u16 buf_len, swid;
int status, i;
@ -1192,7 +1192,7 @@ ice_lag_set_swid(u16 primary_swid, struct ice_lag *local_lag,
else
swid = local_lag->pf->hw.port_info->sw_id;
cmd = &desc.params.set_port_params;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);
cmd->swid = cpu_to_le16(ICE_AQC_PORT_SWID_VALID | swid);

10
drivers/net/ethernet/intel/ice/ice_lib.c
View File

@ -3736,20 +3736,20 @@ int ice_set_link(struct ice_vsi *vsi, bool ena)
status = ice_aq_set_link_restart_an(pi, ena, NULL);
/* if link is owned by manageability, FW will return ICE_AQ_RC_EMODE.
/* if link is owned by manageability, FW will return LIBIE_AQ_RC_EMODE.
* this is not a fatal error, so print a warning message and return
* a success code. Return an error if FW returns an error code other
* than ICE_AQ_RC_EMODE
* than LIBIE_AQ_RC_EMODE
*/
if (status == -EIO) {
if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE)
dev_dbg(dev, "can't set link to %s, err %d aq_err %s. not fatal, continuing\n",
(ena ? "ON" : "OFF"), status,
ice_aq_str(hw->adminq.sq_last_status));
libie_aq_str(hw->adminq.sq_last_status));
} else if (status) {
dev_err(dev, "can't set link to %s, err %d aq_err %s\n",
(ena ? "ON" : "OFF"), status,
ice_aq_str(hw->adminq.sq_last_status));
libie_aq_str(hw->adminq.sq_last_status));
return status;
}

67
drivers/net/ethernet/intel/ice/ice_main.c
View File

@ -38,6 +38,7 @@ static const char ice_copyright[] = "Copyright (c) 2018, Intel Corporation.";
MODULE_DESCRIPTION(DRV_SUMMARY);
MODULE_IMPORT_NS("LIBIE");
MODULE_IMPORT_NS("LIBIE_ADMINQ");
MODULE_LICENSE("GPL v2");
MODULE_FIRMWARE(ICE_DDP_PKG_FILE);
@ -379,7 +380,7 @@ static int ice_vsi_sync_fltr(struct ice_vsi *vsi)
* should go into promiscuous mode. There should be some
* space reserved for promiscuous filters.
*/
if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOSPC &&
if (hw->adminq.sq_last_status == LIBIE_AQ_RC_ENOSPC &&
!test_and_set_bit(ICE_FLTR_OVERFLOW_PROMISC,
vsi->state)) {
promisc_forced_on = true;
@ -1119,7 +1120,7 @@ ice_link_event(struct ice_pf *pf, struct ice_port_info *pi, bool link_up,
if (status)
dev_dbg(dev, "Failed to update link status on port %d, err %d aq_err %s\n",
pi->lport, status,
ice_aq_str(pi->hw->adminq.sq_last_status));
libie_aq_str(pi->hw->adminq.sq_last_status));
ice_check_link_cfg_err(pf, pi->phy.link_info.link_cfg_err);
@ -4224,7 +4225,7 @@ static void ice_set_safe_mode_vlan_cfg(struct ice_pf *pf)
status = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (status) {
dev_err(ice_pf_to_dev(vsi->back), "Failed to update VSI for safe mode VLANs, err %d aq_err %s\n",
status, ice_aq_str(hw->adminq.sq_last_status));
status, libie_aq_str(hw->adminq.sq_last_status));
} else {
vsi->info.sec_flags = ctxt->info.sec_flags;
vsi->info.sw_flags2 = ctxt->info.sw_flags2;
@ -5431,7 +5432,7 @@ static void ice_setup_mc_magic_wake(struct ice_pf *pf)
status = ice_aq_manage_mac_write(hw, mac_addr, flags, NULL);
if (status)
dev_err(dev, "Failed to enable Multicast Magic Packet wake, err %d aq_err %s\n",
status, ice_aq_str(hw->adminq.sq_last_status));
status, libie_aq_str(hw->adminq.sq_last_status));
}
/**
@ -7910,52 +7911,6 @@ int ice_change_mtu(struct net_device *netdev, int new_mtu)
return err;
}
/**
* ice_aq_str - convert AQ err code to a string
* @aq_err: the AQ error code to convert
*/
const char *ice_aq_str(enum ice_aq_err aq_err)
{
switch (aq_err) {
case ICE_AQ_RC_OK:
return "OK";
case ICE_AQ_RC_EPERM:
return "ICE_AQ_RC_EPERM";
case ICE_AQ_RC_ENOENT:
return "ICE_AQ_RC_ENOENT";
case ICE_AQ_RC_ESRCH:
return "ICE_AQ_RC_ESRCH";
case ICE_AQ_RC_EAGAIN:
return "ICE_AQ_RC_EAGAIN";
case ICE_AQ_RC_ENOMEM:
return "ICE_AQ_RC_ENOMEM";
case ICE_AQ_RC_EBUSY:
return "ICE_AQ_RC_EBUSY";
case ICE_AQ_RC_EEXIST:
return "ICE_AQ_RC_EEXIST";
case ICE_AQ_RC_EINVAL:
return "ICE_AQ_RC_EINVAL";
case ICE_AQ_RC_ENOSPC:
return "ICE_AQ_RC_ENOSPC";
case ICE_AQ_RC_ENOSYS:
return "ICE_AQ_RC_ENOSYS";
case ICE_AQ_RC_EMODE:
return "ICE_AQ_RC_EMODE";
case ICE_AQ_RC_ENOSEC:
return "ICE_AQ_RC_ENOSEC";
case ICE_AQ_RC_EBADSIG:
return "ICE_AQ_RC_EBADSIG";
case ICE_AQ_RC_ESVN:
return "ICE_AQ_RC_ESVN";
case ICE_AQ_RC_EBADMAN:
return "ICE_AQ_RC_EBADMAN";
case ICE_AQ_RC_EBADBUF:
return "ICE_AQ_RC_EBADBUF";
}
return "ICE_AQ_RC_UNKNOWN";
}
/**
* ice_set_rss_lut - Set RSS LUT
* @vsi: Pointer to VSI structure
@ -7981,7 +7936,7 @@ int ice_set_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size)
status = ice_aq_set_rss_lut(hw, &params);
if (status)
dev_err(ice_pf_to_dev(vsi->back), "Cannot set RSS lut, err %d aq_err %s\n",
status, ice_aq_str(hw->adminq.sq_last_status));
status, libie_aq_str(hw->adminq.sq_last_status));
return status;
}
@ -8004,7 +7959,7 @@ int ice_set_rss_key(struct ice_vsi *vsi, u8 *seed)
status = ice_aq_set_rss_key(hw, vsi->idx, (struct ice_aqc_get_set_rss_keys *)seed);
if (status)
dev_err(ice_pf_to_dev(vsi->back), "Cannot set RSS key, err %d aq_err %s\n",
status, ice_aq_str(hw->adminq.sq_last_status));
status, libie_aq_str(hw->adminq.sq_last_status));
return status;
}
@ -8034,7 +7989,7 @@ int ice_get_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size)
status = ice_aq_get_rss_lut(hw, &params);
if (status)
dev_err(ice_pf_to_dev(vsi->back), "Cannot get RSS lut, err %d aq_err %s\n",
status, ice_aq_str(hw->adminq.sq_last_status));
status, libie_aq_str(hw->adminq.sq_last_status));
return status;
}
@ -8057,7 +8012,7 @@ int ice_get_rss_key(struct ice_vsi *vsi, u8 *seed)
status = ice_aq_get_rss_key(hw, vsi->idx, (struct ice_aqc_get_set_rss_keys *)seed);
if (status)
dev_err(ice_pf_to_dev(vsi->back), "Cannot get RSS key, err %d aq_err %s\n",
status, ice_aq_str(hw->adminq.sq_last_status));
status, libie_aq_str(hw->adminq.sq_last_status));
return status;
}
@ -8174,7 +8129,7 @@ static int ice_vsi_update_bridge_mode(struct ice_vsi *vsi, u16 bmode)
ret = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (ret) {
dev_err(ice_pf_to_dev(vsi->back), "update VSI for bridge mode failed, bmode = %d err %d aq_err %s\n",
bmode, ret, ice_aq_str(hw->adminq.sq_last_status));
bmode, ret, libie_aq_str(hw->adminq.sq_last_status));
goto out;
}
/* Update sw flags for book keeping */
@ -8242,7 +8197,7 @@ ice_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
if (err) {
netdev_err(dev, "switch rule update failed, mode = %d err %d aq_err %s\n",
mode, err,
ice_aq_str(hw->adminq.sq_last_status));
libie_aq_str(hw->adminq.sq_last_status));
/* revert hw->evb_veb */
hw->evb_veb = (pf_sw->bridge_mode == BRIDGE_MODE_VEB);
return err;

38
drivers/net/ethernet/intel/ice/ice_nvm.c
View File

@ -22,10 +22,10 @@ int ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
u16 length, void *data, bool last_command,
bool read_shadow_ram, struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
struct libie_aq_desc desc;
struct ice_aqc_nvm *cmd;
cmd = &desc.params.nvm;
cmd = libie_aq_raw(&desc);
if (offset > ICE_AQC_NVM_MAX_OFFSET)
return -EINVAL;
@ -125,10 +125,10 @@ ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
u16 length, void *data, bool last_command, u8 command_flags,
struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
struct libie_aq_desc desc;
struct ice_aqc_nvm *cmd;
cmd = &desc.params.nvm;
cmd = libie_aq_raw(&desc);
/* In offset the highest byte must be zeroed. */
if (offset & 0xFF000000)
@ -146,7 +146,7 @@ ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
cmd->offset_high = (offset >> 16) & 0xFF;
cmd->length = cpu_to_le16(length);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
return ice_aq_send_cmd(hw, &desc, data, length, cd);
}
@ -161,10 +161,10 @@ ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
*/
int ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
struct libie_aq_desc desc;
struct ice_aqc_nvm *cmd;
cmd = &desc.params.nvm;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_erase);
@ -869,7 +869,7 @@ static int ice_discover_flash_size(struct ice_hw *hw)
status = ice_read_flat_nvm(hw, offset, &len, &data, false);
if (status == -EIO &&
hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
hw->adminq.sq_last_status == LIBIE_AQ_RC_EINVAL) {
ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
__func__, offset);
status = 0;
@ -1182,14 +1182,14 @@ int ice_init_nvm(struct ice_hw *hw)
int ice_nvm_validate_checksum(struct ice_hw *hw)
{
struct ice_aqc_nvm_checksum *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
status = ice_acquire_nvm(hw, ICE_RES_READ);
if (status)
return status;
cmd = &desc.params.nvm_checksum;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
@ -1226,11 +1226,11 @@ int ice_nvm_validate_checksum(struct ice_hw *hw)
*/
int ice_nvm_write_activate(struct ice_hw *hw, u16 cmd_flags, u8 *response_flags)
{
struct libie_aq_desc desc;
struct ice_aqc_nvm *cmd;
struct ice_aq_desc desc;
int err;
cmd = &desc.params.nvm;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write_activate);
cmd->cmd_flags = (u8)(cmd_flags & 0xFF);
@ -1252,7 +1252,7 @@ int ice_nvm_write_activate(struct ice_hw *hw, u16 cmd_flags, u8 *response_flags)
*/
int ice_aq_nvm_update_empr(struct ice_hw *hw)
{
struct ice_aq_desc desc;
struct libie_aq_desc desc;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_update_empr);
@ -1278,15 +1278,15 @@ ice_nvm_set_pkg_data(struct ice_hw *hw, bool del_pkg_data_flag, u8 *data,
u16 length, struct ice_sq_cd *cd)
{
struct ice_aqc_nvm_pkg_data *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
if (length != 0 && !data)
return -EINVAL;
cmd = &desc.params.pkg_data;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_pkg_data);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
if (del_pkg_data_flag)
cmd->cmd_flags |= ICE_AQC_NVM_PKG_DELETE;
@ -1316,17 +1316,17 @@ ice_nvm_pass_component_tbl(struct ice_hw *hw, u8 *data, u16 length,
u8 *comp_response_code, struct ice_sq_cd *cd)
{
struct ice_aqc_nvm_pass_comp_tbl *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
if (!data || !comp_response || !comp_response_code)
return -EINVAL;
cmd = &desc.params.pass_comp_tbl;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc,
ice_aqc_opc_nvm_pass_component_tbl);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
cmd->transfer_flag = transfer_flag;
status = ice_aq_send_cmd(hw, &desc, data, length, cd);

16
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
View File

@ -424,7 +424,7 @@ static int ice_write_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 val)
};
int err;
err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
if (err)
ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
err);
@ -451,7 +451,7 @@ static int ice_read_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 *val)
};
int err;
err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
if (err)
ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
err);
@ -2348,7 +2348,7 @@ ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
ice_fill_phy_msg_e82x(hw, &msg, port, offset);
msg.opcode = ice_sbq_msg_rd;
err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
err);
@ -2426,7 +2426,7 @@ ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val)
msg.opcode = ice_sbq_msg_wr;
msg.data = val;
err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
err);
@ -2587,7 +2587,7 @@ ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)
msg.opcode = ice_sbq_msg_rd;
err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
err);
@ -2622,7 +2622,7 @@ ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
msg.opcode = ice_sbq_msg_wr;
msg.data = val;
err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
err);
@ -4267,7 +4267,7 @@ static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)
msg.opcode = ice_sbq_msg_rd;
msg.dest_dev = ice_sbq_dev_phy_0;
err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
err);
@ -4298,7 +4298,7 @@ static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)
msg.dest_dev = ice_sbq_dev_phy_0;
msg.data = val;
err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
err);

18
drivers/net/ethernet/intel/ice/ice_sched.c
View File

@ -123,13 +123,13 @@ ice_aqc_send_sched_elem_cmd(struct ice_hw *hw, enum ice_adminq_opc cmd_opc,
u16 *elems_resp, struct ice_sq_cd *cd)
{
struct ice_aqc_sched_elem_cmd *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
cmd = &desc.params.sched_elem_cmd;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, cmd_opc);
cmd->num_elem_req = cpu_to_le16(elems_req);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
if (!status && elems_resp)
*elems_resp = le16_to_cpu(cmd->num_elem_resp);
@ -392,10 +392,10 @@ ice_aq_get_dflt_topo(struct ice_hw *hw, u8 lport,
u8 *num_branches, struct ice_sq_cd *cd)
{
struct ice_aqc_get_topo *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
cmd = &desc.params.get_topo;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_dflt_topo);
cmd->port_num = lport;
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
@ -518,7 +518,7 @@ ice_aq_query_sched_res(struct ice_hw *hw, u16 buf_size,
struct ice_aqc_query_txsched_res_resp *buf,
struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
struct libie_aq_desc desc;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_sched_res);
return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
@ -683,13 +683,13 @@ ice_aq_rl_profile(struct ice_hw *hw, enum ice_adminq_opc opcode,
u16 buf_size, u16 *num_processed, struct ice_sq_cd *cd)
{
struct ice_aqc_rl_profile *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
cmd = &desc.params.rl_profile;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, opcode);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
cmd->num_profiles = cpu_to_le16(num_profiles);
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
if (!status && num_processed)

4
drivers/net/ethernet/intel/ice/ice_sriov.c
View File

@ -1161,10 +1161,12 @@ static u32 ice_globalq_to_pfq(struct ice_pf *pf, u32 globalq)
void
ice_vf_lan_overflow_event(struct ice_pf *pf, struct ice_rq_event_info *event)
{
struct ice_aqc_event_lan_overflow *cmd;
u32 gldcb_rtctq, queue;
struct ice_vf *vf;
gldcb_rtctq = le32_to_cpu(event->desc.params.lan_overflow.prtdcb_ruptq);
cmd = libie_aq_raw(&event->desc);
gldcb_rtctq = le32_to_cpu(cmd->prtdcb_ruptq);
dev_dbg(ice_pf_to_dev(pf), "GLDCB_RTCTQ: 0x%08x\n", gldcb_rtctq);
/* event returns device global Rx queue number */

55
drivers/net/ethernet/intel/ice/ice_switch.c
View File

@ -1511,11 +1511,11 @@ ice_aq_get_sw_cfg(struct ice_hw *hw, struct ice_aqc_get_sw_cfg_resp_elem *buf,
struct ice_sq_cd *cd)
{
struct ice_aqc_get_sw_cfg *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sw_cfg);
cmd = &desc.params.get_sw_conf;
cmd = libie_aq_raw(&desc);
cmd->element = cpu_to_le16(*req_desc);
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
@ -1541,11 +1541,11 @@ ice_aq_add_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,
{
struct ice_aqc_add_update_free_vsi_resp *res;
struct ice_aqc_add_get_update_free_vsi *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
cmd = &desc.params.vsi_cmd;
res = &desc.params.add_update_free_vsi_res;
cmd = libie_aq_raw(&desc);
res = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_vsi);
@ -1556,7 +1556,7 @@ ice_aq_add_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,
cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
status = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info,
sizeof(vsi_ctx->info), cd);
@ -1585,11 +1585,11 @@ ice_aq_free_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,
{
struct ice_aqc_add_update_free_vsi_resp *resp;
struct ice_aqc_add_get_update_free_vsi *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
cmd = &desc.params.vsi_cmd;
resp = &desc.params.add_update_free_vsi_res;
cmd = libie_aq_raw(&desc);
resp = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_free_vsi);
@ -1620,17 +1620,17 @@ ice_aq_update_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,
{
struct ice_aqc_add_update_free_vsi_resp *resp;
struct ice_aqc_add_get_update_free_vsi *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
cmd = &desc.params.vsi_cmd;
resp = &desc.params.add_update_free_vsi_res;
cmd = libie_aq_raw(&desc);
resp = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_update_vsi);
cmd->vsi_num = cpu_to_le16(vsi_ctx->vsi_num | ICE_AQ_VSI_IS_VALID);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
status = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info,
sizeof(vsi_ctx->info), cd);
@ -1944,7 +1944,8 @@ int
ice_aq_sw_rules(struct ice_hw *hw, void *rule_list, u16 rule_list_sz,
u8 num_rules, enum ice_adminq_opc opc, struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
struct ice_aqc_sw_rules *cmd;
struct libie_aq_desc desc;
int status;
if (opc != ice_aqc_opc_add_sw_rules &&
@ -1953,13 +1954,13 @@ ice_aq_sw_rules(struct ice_hw *hw, void *rule_list, u16 rule_list_sz,
return -EINVAL;
ice_fill_dflt_direct_cmd_desc(&desc, opc);
cmd = libie_aq_raw(&desc);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.params.sw_rules.num_rules_fltr_entry_index =
cpu_to_le16(num_rules);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
cmd->num_rules_fltr_entry_index = cpu_to_le16(num_rules);
status = ice_aq_send_cmd(hw, &desc, rule_list, rule_list_sz, cd);
if (opc != ice_aqc_opc_add_sw_rules &&
hw->adminq.sq_last_status == ICE_AQ_RC_ENOENT)
hw->adminq.sq_last_status == LIBIE_AQ_RC_ENOENT)
status = -ENOENT;
if (!status) {
@ -1989,14 +1990,14 @@ ice_aq_add_recipe(struct ice_hw *hw,
u16 num_recipes, struct ice_sq_cd *cd)
{
struct ice_aqc_add_get_recipe *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
u16 buf_size;
cmd = &desc.params.add_get_recipe;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_recipe);
cmd->num_sub_recipes = cpu_to_le16(num_recipes);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
buf_size = num_recipes * sizeof(*s_recipe_list);
@ -2026,14 +2027,14 @@ ice_aq_get_recipe(struct ice_hw *hw,
u16 *num_recipes, u16 recipe_root, struct ice_sq_cd *cd)
{
struct ice_aqc_add_get_recipe *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
u16 buf_size;
int status;
if (*num_recipes != ICE_MAX_NUM_RECIPES)
return -EINVAL;
cmd = &desc.params.add_get_recipe;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_recipe);
cmd->return_index = cpu_to_le16(recipe_root);
@ -2118,9 +2119,9 @@ ice_aq_map_recipe_to_profile(struct ice_hw *hw, u32 profile_id, u64 r_assoc,
struct ice_sq_cd *cd)
{
struct ice_aqc_recipe_to_profile *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
cmd = &desc.params.recipe_to_profile;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_recipe_to_profile);
cmd->profile_id = cpu_to_le16(profile_id);
/* Set the recipe ID bit in the bitmask to let the device know which
@ -2144,10 +2145,10 @@ ice_aq_get_recipe_to_profile(struct ice_hw *hw, u32 profile_id, u64 *r_assoc,
struct ice_sq_cd *cd)
{
struct ice_aqc_recipe_to_profile *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
int status;
cmd = &desc.params.recipe_to_profile;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_recipe_to_profile);
cmd->profile_id = cpu_to_le16(profile_id);

6
drivers/net/ethernet/intel/ice/ice_vf_mbx.c
View File

@ -23,18 +23,18 @@ ice_aq_send_msg_to_vf(struct ice_hw *hw, u16 vfid, u32 v_opcode, u32 v_retval,
u8 *msg, u16 msglen, struct ice_sq_cd *cd)
{
struct ice_aqc_pf_vf_msg *cmd;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
ice_fill_dflt_direct_cmd_desc(&desc, ice_mbx_opc_send_msg_to_vf);
cmd = &desc.params.virt;
cmd = libie_aq_raw(&desc);
cmd->id = cpu_to_le32(vfid);
desc.cookie_high = cpu_to_le32(v_opcode);
desc.cookie_low = cpu_to_le32(v_retval);
if (msglen)
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
return ice_sq_send_cmd(hw, &hw->mailboxq, &desc, msg, msglen, cd);
}

6
drivers/net/ethernet/intel/ice/ice_virtchnl.c
View File

@ -304,10 +304,10 @@ ice_vc_send_msg_to_vf(struct ice_vf *vf, u32 v_opcode,
aq_ret = ice_aq_send_msg_to_vf(&pf->hw, vf->vf_id, v_opcode, v_retval,
msg, msglen, NULL);
if (aq_ret && pf->hw.mailboxq.sq_last_status != ICE_AQ_RC_ENOSYS) {
if (aq_ret && pf->hw.mailboxq.sq_last_status != LIBIE_AQ_RC_ENOSYS) {
dev_info(dev, "Unable to send the message to VF %d ret %d aq_err %s\n",
vf->vf_id, aq_ret,
ice_aq_str(pf->hw.mailboxq.sq_last_status));
libie_aq_str(pf->hw.mailboxq.sq_last_status));
return -EIO;
}
@ -852,7 +852,7 @@ static int ice_vc_handle_rss_cfg(struct ice_vf *vf, u8 *msg, bool add)
status = ice_update_vsi(hw, vsi->idx, ctx, NULL);
if (status) {
dev_err(dev, "update VSI for RSS failed, err %d aq_err %s\n",
status, ice_aq_str(hw->adminq.sq_last_status));
status, libie_aq_str(hw->adminq.sq_last_status));
v_ret = VIRTCHNL_STATUS_ERR_PARAM;
} else {
vsi->info.q_opt_rss = ctx->info.q_opt_rss;

6
drivers/net/ethernet/intel/ice/ice_vlan_mode.c
View File

@ -63,7 +63,7 @@ static int
ice_aq_get_vlan_mode(struct ice_hw *hw,
struct ice_aqc_get_vlan_mode *get_params)
{
struct ice_aq_desc desc;
struct libie_aq_desc desc;
if (!get_params)
return -EINVAL;
@ -275,7 +275,7 @@ ice_aq_set_vlan_mode(struct ice_hw *hw,
struct ice_aqc_set_vlan_mode *set_params)
{
u8 rdma_packet, mng_vlan_prot_id;
struct ice_aq_desc desc;
struct libie_aq_desc desc;
if (!set_params)
return -EINVAL;
@ -295,7 +295,7 @@ ice_aq_set_vlan_mode(struct ice_hw *hw,
ice_fill_dflt_direct_cmd_desc(&desc,
ice_aqc_opc_set_vlan_mode_parameters);
desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
return ice_aq_send_cmd(hw, &desc, set_params, sizeof(*set_params),
NULL);

24
drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c
View File

@ -113,7 +113,7 @@ static int ice_vsi_manage_vlan_insertion(struct ice_vsi *vsi)
err = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (err) {
dev_err(ice_pf_to_dev(vsi->back), "update VSI for VLAN insert failed, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
goto out;
}
@ -169,7 +169,7 @@ static int ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
err = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (err) {
dev_err(ice_pf_to_dev(vsi->back), "update VSI for VLAN strip failed, ena = %d err %d aq_err %s\n",
ena, err, ice_aq_str(hw->adminq.sq_last_status));
ena, err, libie_aq_str(hw->adminq.sq_last_status));
goto out;
}
@ -258,7 +258,7 @@ static int __ice_vsi_set_inner_port_vlan(struct ice_vsi *vsi, u16 pvid_info)
ret = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (ret) {
dev_info(ice_hw_to_dev(hw), "update VSI for port VLAN failed, err %d aq_err %s\n",
ret, ice_aq_str(hw->adminq.sq_last_status));
ret, libie_aq_str(hw->adminq.sq_last_status));
goto out;
}
@ -306,7 +306,7 @@ int ice_vsi_clear_inner_port_vlan(struct ice_vsi *vsi)
ret = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (ret)
dev_err(ice_hw_to_dev(hw), "update VSI for port VLAN failed, err %d aq_err %s\n",
ret, ice_aq_str(hw->adminq.sq_last_status));
ret, libie_aq_str(hw->adminq.sq_last_status));
kfree(ctxt);
return ret;
@ -353,7 +353,7 @@ static int ice_cfg_vlan_pruning(struct ice_vsi *vsi, bool ena)
if (status) {
netdev_err(vsi->netdev, "%sabling VLAN pruning on VSI handle: %d, VSI HW ID: %d failed, err = %d, aq_err = %s\n",
ena ? "En" : "Dis", vsi->idx, vsi->vsi_num, status,
ice_aq_str(pf->hw.adminq.sq_last_status));
libie_aq_str(pf->hw.adminq.sq_last_status));
goto err_out;
}
@ -497,7 +497,7 @@ int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi, u16 tpid)
err = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (err)
dev_err(ice_pf_to_dev(vsi->back), "update VSI for enabling outer VLAN stripping failed, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
else
vsi->info.outer_vlan_flags = ctxt->info.outer_vlan_flags;
@ -544,7 +544,7 @@ int ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
err = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (err)
dev_err(ice_pf_to_dev(vsi->back), "update VSI for disabling outer VLAN stripping failed, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
else
vsi->info.outer_vlan_flags = ctxt->info.outer_vlan_flags;
@ -604,7 +604,7 @@ int ice_vsi_ena_outer_insertion(struct ice_vsi *vsi, u16 tpid)
err = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (err)
dev_err(ice_pf_to_dev(vsi->back), "update VSI for enabling outer VLAN insertion failed, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
else
vsi->info.outer_vlan_flags = ctxt->info.outer_vlan_flags;
@ -654,7 +654,7 @@ int ice_vsi_dis_outer_insertion(struct ice_vsi *vsi)
err = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (err)
dev_err(ice_pf_to_dev(vsi->back), "update VSI for disabling outer VLAN insertion failed, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
else
vsi->info.outer_vlan_flags = ctxt->info.outer_vlan_flags;
@ -720,7 +720,7 @@ __ice_vsi_set_outer_port_vlan(struct ice_vsi *vsi, u16 vlan_info, u16 tpid)
err = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (err) {
dev_err(ice_pf_to_dev(vsi->back), "update VSI for setting outer port based VLAN failed, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
} else {
vsi->info.port_based_outer_vlan = ctxt->info.port_based_outer_vlan;
vsi->info.outer_vlan_flags = ctxt->info.outer_vlan_flags;
@ -782,7 +782,7 @@ int ice_vsi_clear_outer_port_vlan(struct ice_vsi *vsi)
err = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (err)
dev_err(ice_pf_to_dev(vsi->back), "update VSI for clearing outer port based VLAN failed, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
kfree(ctxt);
return err;
@ -830,7 +830,7 @@ int ice_vsi_clear_port_vlan(struct ice_vsi *vsi)
err = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
if (err) {
dev_err(ice_pf_to_dev(vsi->back), "update VSI for clearing port based VLAN failed, err %d aq_err %s\n",
err, ice_aq_str(hw->adminq.sq_last_status));
err, libie_aq_str(hw->adminq.sq_last_status));
} else {
vsi->info.port_based_outer_vlan =
ctxt->info.port_based_outer_vlan;

4
drivers/net/ethernet/intel/ixgbe/devlink/region.c
View File

@ -74,7 +74,7 @@ static int ixgbe_devlink_nvm_snapshot(struct devlink *devlink,
* total period of reading whole NVM is longer than the maximum
* period the lock can be taken defined by the IXGBE_NVM_TIMEOUT.
*/
err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);
err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ);
if (err) {
NL_SET_ERR_MSG_MOD(extack,
"Failed to acquire NVM semaphore");
@ -184,7 +184,7 @@ static int ixgbe_devlink_nvm_read(struct devlink *devlink,
return -ERANGE;
}
err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);
err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ);
if (err) {
NL_SET_ERR_MSG_MOD(extack, "Failed to acquire NVM semaphore");
return -EBUSY;

272
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
View File

@ -56,7 +56,7 @@ static bool ixgbe_should_retry_aci_send_cmd_execute(u16 opcode)
* Admin Command failed with error Y.
*/
static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw,
struct ixgbe_aci_desc *desc,
struct libie_aq_desc *desc,
void *buf, u16 buf_size)
{
u16 opcode, buf_tail_size = buf_size % 4;
@ -64,7 +64,7 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw,
u32 hicr, i, buf_tail = 0;
bool valid_buf = false;
hw->aci.last_status = IXGBE_ACI_RC_OK;
hw->aci.last_status = LIBIE_AQ_RC_OK;
/* It's necessary to check if mechanism is enabled */
hicr = IXGBE_READ_REG(hw, IXGBE_PF_HICR);
@ -73,7 +73,7 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw,
return -EIO;
if (hicr & IXGBE_PF_HICR_C) {
hw->aci.last_status = IXGBE_ACI_RC_EBUSY;
hw->aci.last_status = LIBIE_AQ_RC_EBUSY;
return -EBUSY;
}
@ -83,9 +83,9 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw,
return -EINVAL;
if (buf)
desc->flags |= cpu_to_le16(IXGBE_ACI_FLAG_BUF);
desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF);
if (desc->flags & cpu_to_le16(IXGBE_ACI_FLAG_BUF)) {
if (desc->flags & cpu_to_le16(LIBIE_AQ_FLAG_BUF)) {
if ((buf && !buf_size) ||
(!buf && buf_size))
return -EINVAL;
@ -98,12 +98,12 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw,
memcpy(&buf_tail, buf + buf_size - buf_tail_size,
buf_tail_size);
if (((buf_size + 3) & ~0x3) > IXGBE_ACI_LG_BUF)
desc->flags |= cpu_to_le16(IXGBE_ACI_FLAG_LB);
if (((buf_size + 3) & ~0x3) > LIBIE_AQ_LG_BUF)
desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB);
desc->datalen = cpu_to_le16(buf_size);
if (desc->flags & cpu_to_le16(IXGBE_ACI_FLAG_RD)) {
if (desc->flags & cpu_to_le16(LIBIE_AQ_FLAG_RD)) {
for (i = 0; i < buf_size / 4; i++)
IXGBE_WRITE_REG(hw, IXGBE_PF_HIBA(i), ((u32 *)buf)[i]);
if (buf_tail_size)
@ -174,7 +174,7 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw,
return -EIO;
if (desc->retval) {
hw->aci.last_status = (enum ixgbe_aci_err)
hw->aci.last_status = (enum libie_aq_err)
le16_to_cpu(desc->retval);
return -EIO;
}
@ -207,12 +207,12 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw,
*
* Return: the exit code of the operation.
*/
int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc,
int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct libie_aq_desc *desc,
void *buf, u16 buf_size)
{
u16 opcode = le16_to_cpu(desc->opcode);
struct ixgbe_aci_desc desc_cpy;
enum ixgbe_aci_err last_status;
struct libie_aq_desc desc_cpy;
enum libie_aq_err last_status;
u8 idx = 0, *buf_cpy = NULL;
bool is_cmd_for_retry;
unsigned long timeout;
@ -237,7 +237,7 @@ int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc,
mutex_unlock(&hw->aci.lock);
if (!is_cmd_for_retry || !err ||
last_status != IXGBE_ACI_RC_EBUSY)
last_status != LIBIE_AQ_RC_EBUSY)
break;
if (buf)
@ -286,7 +286,7 @@ bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw)
int ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e,
bool *pending)
{
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
int err;
if (!e || (!e->msg_buf && e->buf_len))
@ -335,12 +335,12 @@ int ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e,
* Helper function to fill the descriptor desc with default values
* and the provided opcode.
*/
void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode)
void ixgbe_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode)
{
/* Zero out the desc. */
memset(desc, 0, sizeof(*desc));
desc->opcode = cpu_to_le16(opcode);
desc->flags = cpu_to_le16(IXGBE_ACI_FLAG_SI);
desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI);
}
/**
@ -353,8 +353,8 @@ void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode)
*/
static int ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw)
{
struct ixgbe_aci_cmd_get_ver *resp;
struct ixgbe_aci_desc desc;
struct libie_aqc_get_ver *resp;
struct libie_aq_desc desc;
int err;
resp = &desc.params.get_ver;
@ -393,12 +393,12 @@ static int ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw)
*
* Return: the exit code of the operation.
*/
static int ixgbe_aci_req_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,
enum ixgbe_aci_res_access_type access,
static int ixgbe_aci_req_res(struct ixgbe_hw *hw, enum libie_aq_res_id res,
enum libie_aq_res_access_type access,
u8 sdp_number, u32 *timeout)
{
struct ixgbe_aci_cmd_req_res *cmd_resp;
struct ixgbe_aci_desc desc;
struct libie_aqc_req_res *cmd_resp;
struct libie_aq_desc desc;
int err;
cmd_resp = &desc.params.res_owner;
@ -417,7 +417,7 @@ static int ixgbe_aci_req_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,
* with a busy return value and the timeout field indicates the maximum
* time the current owner of the resource has to free it.
*/
if (!err || hw->aci.last_status == IXGBE_ACI_RC_EBUSY)
if (!err || hw->aci.last_status == LIBIE_AQ_RC_EBUSY)
*timeout = le32_to_cpu(cmd_resp->timeout);
return err;
@ -433,11 +433,11 @@ static int ixgbe_aci_req_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,
*
* Return: the exit code of the operation.
*/
static int ixgbe_aci_release_res(struct ixgbe_hw *hw,
enum ixgbe_aci_res_ids res, u8 sdp_number)
static int ixgbe_aci_release_res(struct ixgbe_hw *hw, enum libie_aq_res_id res,
u8 sdp_number)
{
struct ixgbe_aci_cmd_req_res *cmd;
struct ixgbe_aci_desc desc;
struct libie_aqc_req_res *cmd;
struct libie_aq_desc desc;
cmd = &desc.params.res_owner;
@ -465,8 +465,8 @@ static int ixgbe_aci_release_res(struct ixgbe_hw *hw,
*
* Return: the exit code of the operation.
*/
int ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,
enum ixgbe_aci_res_access_type access, u32 timeout)
int ixgbe_acquire_res(struct ixgbe_hw *hw, enum libie_aq_res_id res,
enum libie_aq_res_access_type access, u32 timeout)
{
#define IXGBE_RES_POLLING_DELAY_MS 10
u32 delay = IXGBE_RES_POLLING_DELAY_MS;
@ -514,7 +514,7 @@ int ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,
*
* Release a common resource using ixgbe_aci_release_res.
*/
void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res)
void ixgbe_release_res(struct ixgbe_hw *hw, enum libie_aq_res_id res)
{
u32 total_delay = 0;
int err;
@ -547,7 +547,7 @@ void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res)
*/
static bool ixgbe_parse_e610_caps(struct ixgbe_hw *hw,
struct ixgbe_hw_caps *caps,
struct ixgbe_aci_cmd_list_caps_elem *elem,
struct libie_aqc_list_caps_elem *elem,
const char *prefix)
{
u32 logical_id = le32_to_cpu(elem->logical_id);
@ -556,67 +556,67 @@ static bool ixgbe_parse_e610_caps(struct ixgbe_hw *hw,
u16 cap = le16_to_cpu(elem->cap);
switch (cap) {
case IXGBE_ACI_CAPS_VALID_FUNCTIONS:
case LIBIE_AQC_CAPS_VALID_FUNCTIONS:
caps->valid_functions = number;
break;
case IXGBE_ACI_CAPS_SRIOV:
case LIBIE_AQC_CAPS_SRIOV:
caps->sr_iov_1_1 = (number == 1);
break;
case IXGBE_ACI_CAPS_VMDQ:
case LIBIE_AQC_CAPS_VMDQ:
caps->vmdq = (number == 1);
break;
case IXGBE_ACI_CAPS_DCB:
case LIBIE_AQC_CAPS_DCB:
caps->dcb = (number == 1);
caps->active_tc_bitmap = logical_id;
caps->maxtc = phys_id;
break;
case IXGBE_ACI_CAPS_RSS:
case LIBIE_AQC_CAPS_RSS:
caps->rss_table_size = number;
caps->rss_table_entry_width = logical_id;
break;
case IXGBE_ACI_CAPS_RXQS:
case LIBIE_AQC_CAPS_RXQS:
caps->num_rxq = number;
caps->rxq_first_id = phys_id;
break;
case IXGBE_ACI_CAPS_TXQS:
case LIBIE_AQC_CAPS_TXQS:
caps->num_txq = number;
caps->txq_first_id = phys_id;
break;
case IXGBE_ACI_CAPS_MSIX:
case LIBIE_AQC_CAPS_MSIX:
caps->num_msix_vectors = number;
caps->msix_vector_first_id = phys_id;
break;
case IXGBE_ACI_CAPS_NVM_VER:
case LIBIE_AQC_CAPS_NVM_VER:
break;
case IXGBE_ACI_CAPS_PENDING_NVM_VER:
case LIBIE_AQC_CAPS_PENDING_NVM_VER:
caps->nvm_update_pending_nvm = true;
break;
case IXGBE_ACI_CAPS_PENDING_OROM_VER:
case LIBIE_AQC_CAPS_PENDING_OROM_VER:
caps->nvm_update_pending_orom = true;
break;
case IXGBE_ACI_CAPS_PENDING_NET_VER:
case LIBIE_AQC_CAPS_PENDING_NET_VER:
caps->nvm_update_pending_netlist = true;
break;
case IXGBE_ACI_CAPS_NVM_MGMT:
case LIBIE_AQC_CAPS_NVM_MGMT:
caps->nvm_unified_update =
(number & IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
true : false;
break;
case IXGBE_ACI_CAPS_MAX_MTU:
case LIBIE_AQC_CAPS_MAX_MTU:
caps->max_mtu = number;
break;
case IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE:
case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE:
caps->pcie_reset_avoidance = (number > 0);
break;
case IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT:
case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:
caps->reset_restrict_support = (number == 1);
break;
case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0:
case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1:
case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2:
case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3:
case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG0:
case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG1:
case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG2:
case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG3:
{
u8 index = cap - IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0;
u8 index = cap - LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG0;
caps->ext_topo_dev_img_ver_high[index] = number;
caps->ext_topo_dev_img_ver_low[index] = logical_id;
@ -637,62 +637,62 @@ static bool ixgbe_parse_e610_caps(struct ixgbe_hw *hw,
}
/**
* ixgbe_parse_valid_functions_cap - Parse IXGBE_ACI_CAPS_VALID_FUNCTIONS caps
* ixgbe_parse_valid_functions_cap - Parse LIBIE_AQC_CAPS_VALID_FUNCTIONS caps
* @hw: pointer to the HW struct
* @dev_p: pointer to device capabilities structure
* @cap: capability element to parse
*
* Parse IXGBE_ACI_CAPS_VALID_FUNCTIONS for device capabilities.
* Parse LIBIE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
*/
static void
ixgbe_parse_valid_functions_cap(struct ixgbe_hw *hw,
struct ixgbe_hw_dev_caps *dev_p,
struct ixgbe_aci_cmd_list_caps_elem *cap)
struct libie_aqc_list_caps_elem *cap)
{
dev_p->num_funcs = hweight32(le32_to_cpu(cap->number));
}
/**
* ixgbe_parse_vf_dev_caps - Parse IXGBE_ACI_CAPS_VF device caps
* ixgbe_parse_vf_dev_caps - Parse LIBIE_AQC_CAPS_VF device caps
* @hw: pointer to the HW struct
* @dev_p: pointer to device capabilities structure
* @cap: capability element to parse
*
* Parse IXGBE_ACI_CAPS_VF for device capabilities.
* Parse LIBIE_AQC_CAPS_VF for device capabilities.
*/
static void ixgbe_parse_vf_dev_caps(struct ixgbe_hw *hw,
struct ixgbe_hw_dev_caps *dev_p,
struct ixgbe_aci_cmd_list_caps_elem *cap)
struct libie_aqc_list_caps_elem *cap)
{
dev_p->num_vfs_exposed = le32_to_cpu(cap->number);
}
/**
* ixgbe_parse_vsi_dev_caps - Parse IXGBE_ACI_CAPS_VSI device caps
* ixgbe_parse_vsi_dev_caps - Parse LIBIE_AQC_CAPS_VSI device caps
* @hw: pointer to the HW struct
* @dev_p: pointer to device capabilities structure
* @cap: capability element to parse
*
* Parse IXGBE_ACI_CAPS_VSI for device capabilities.
* Parse LIBIE_AQC_CAPS_VSI for device capabilities.
*/
static void ixgbe_parse_vsi_dev_caps(struct ixgbe_hw *hw,
struct ixgbe_hw_dev_caps *dev_p,
struct ixgbe_aci_cmd_list_caps_elem *cap)
struct libie_aqc_list_caps_elem *cap)
{
dev_p->num_vsi_allocd_to_host = le32_to_cpu(cap->number);
}
/**
* ixgbe_parse_fdir_dev_caps - Parse IXGBE_ACI_CAPS_FD device caps
* ixgbe_parse_fdir_dev_caps - Parse LIBIE_AQC_CAPS_FD device caps
* @hw: pointer to the HW struct
* @dev_p: pointer to device capabilities structure
* @cap: capability element to parse
*
* Parse IXGBE_ACI_CAPS_FD for device capabilities.
* Parse LIBIE_AQC_CAPS_FD for device capabilities.
*/
static void ixgbe_parse_fdir_dev_caps(struct ixgbe_hw *hw,
struct ixgbe_hw_dev_caps *dev_p,
struct ixgbe_aci_cmd_list_caps_elem *cap)
struct libie_aqc_list_caps_elem *cap)
{
dev_p->num_flow_director_fltr = le32_to_cpu(cap->number);
}
@ -715,10 +715,10 @@ static void ixgbe_parse_dev_caps(struct ixgbe_hw *hw,
struct ixgbe_hw_dev_caps *dev_p,
void *buf, u32 cap_count)
{
struct ixgbe_aci_cmd_list_caps_elem *cap_resp;
struct libie_aqc_list_caps_elem *cap_resp;
u32 i;
cap_resp = (struct ixgbe_aci_cmd_list_caps_elem *)buf;
cap_resp = (struct libie_aqc_list_caps_elem *)buf;
memset(dev_p, 0, sizeof(*dev_p));
@ -729,17 +729,17 @@ static void ixgbe_parse_dev_caps(struct ixgbe_hw *hw,
"dev caps");
switch (cap) {
case IXGBE_ACI_CAPS_VALID_FUNCTIONS:
case LIBIE_AQC_CAPS_VALID_FUNCTIONS:
ixgbe_parse_valid_functions_cap(hw, dev_p,
&cap_resp[i]);
break;
case IXGBE_ACI_CAPS_VF:
case LIBIE_AQC_CAPS_VF:
ixgbe_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]);
break;
case IXGBE_ACI_CAPS_VSI:
case LIBIE_AQC_CAPS_VSI:
ixgbe_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
break;
case IXGBE_ACI_CAPS_FD:
case LIBIE_AQC_CAPS_FD:
ixgbe_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
break;
default:
@ -750,16 +750,16 @@ static void ixgbe_parse_dev_caps(struct ixgbe_hw *hw,
}
/**
* ixgbe_parse_vf_func_caps - Parse IXGBE_ACI_CAPS_VF function caps
* ixgbe_parse_vf_func_caps - Parse LIBIE_AQC_CAPS_VF function caps
* @hw: pointer to the HW struct
* @func_p: pointer to function capabilities structure
* @cap: pointer to the capability element to parse
*
* Extract function capabilities for IXGBE_ACI_CAPS_VF.
* Extract function capabilities for LIBIE_AQC_CAPS_VF.
*/
static void ixgbe_parse_vf_func_caps(struct ixgbe_hw *hw,
struct ixgbe_hw_func_caps *func_p,
struct ixgbe_aci_cmd_list_caps_elem *cap)
struct libie_aqc_list_caps_elem *cap)
{
func_p->num_allocd_vfs = le32_to_cpu(cap->number);
func_p->vf_base_id = le32_to_cpu(cap->logical_id);
@ -786,16 +786,16 @@ static u32 ixgbe_get_num_per_func(struct ixgbe_hw *hw, u32 max)
}
/**
* ixgbe_parse_vsi_func_caps - Parse IXGBE_ACI_CAPS_VSI function caps
* ixgbe_parse_vsi_func_caps - Parse LIBIE_AQC_CAPS_VSI function caps
* @hw: pointer to the HW struct
* @func_p: pointer to function capabilities structure
* @cap: pointer to the capability element to parse
*
* Extract function capabilities for IXGBE_ACI_CAPS_VSI.
* Extract function capabilities for LIBIE_AQC_CAPS_VSI.
*/
static void ixgbe_parse_vsi_func_caps(struct ixgbe_hw *hw,
struct ixgbe_hw_func_caps *func_p,
struct ixgbe_aci_cmd_list_caps_elem *cap)
struct libie_aqc_list_caps_elem *cap)
{
func_p->guar_num_vsi = ixgbe_get_num_per_func(hw, IXGBE_MAX_VSI);
}
@ -818,10 +818,10 @@ static void ixgbe_parse_func_caps(struct ixgbe_hw *hw,
struct ixgbe_hw_func_caps *func_p,
void *buf, u32 cap_count)
{
struct ixgbe_aci_cmd_list_caps_elem *cap_resp;
struct libie_aqc_list_caps_elem *cap_resp;
u32 i;
cap_resp = (struct ixgbe_aci_cmd_list_caps_elem *)buf;
cap_resp = (struct libie_aqc_list_caps_elem *)buf;
memset(func_p, 0, sizeof(*func_p));
@ -832,10 +832,10 @@ static void ixgbe_parse_func_caps(struct ixgbe_hw *hw,
&cap_resp[i], "func caps");
switch (cap) {
case IXGBE_ACI_CAPS_VF:
case LIBIE_AQC_CAPS_VF:
ixgbe_parse_vf_func_caps(hw, func_p, &cap_resp[i]);
break;
case IXGBE_ACI_CAPS_VSI:
case LIBIE_AQC_CAPS_VSI:
ixgbe_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
break;
default:
@ -869,8 +869,8 @@ static void ixgbe_parse_func_caps(struct ixgbe_hw *hw,
int ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size,
u32 *cap_count, enum ixgbe_aci_opc opc)
{
struct ixgbe_aci_cmd_list_caps *cmd;
struct ixgbe_aci_desc desc;
struct libie_aqc_list_caps *cmd;
struct libie_aq_desc desc;
int err;
cmd = &desc.params.get_cap;
@ -914,7 +914,7 @@ int ixgbe_discover_dev_caps(struct ixgbe_hw *hw,
* possible size that firmware can return.
*/
cap_count = IXGBE_ACI_MAX_BUFFER_SIZE /
sizeof(struct ixgbe_aci_cmd_list_caps_elem);
sizeof(struct libie_aqc_list_caps_elem);
err = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE,
&cap_count,
@ -953,7 +953,7 @@ int ixgbe_discover_func_caps(struct ixgbe_hw *hw,
* possible size that firmware can return.
*/
cap_count = IXGBE_ACI_MAX_BUFFER_SIZE /
sizeof(struct ixgbe_aci_cmd_list_caps_elem);
sizeof(struct libie_aqc_list_caps_elem);
err = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE,
&cap_count,
@ -996,9 +996,9 @@ int ixgbe_get_caps(struct ixgbe_hw *hw)
int ixgbe_aci_disable_rxen(struct ixgbe_hw *hw)
{
struct ixgbe_aci_cmd_disable_rxen *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
cmd = &desc.params.disable_rxen;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_disable_rxen);
@ -1024,10 +1024,10 @@ int ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode,
{
struct ixgbe_aci_cmd_get_phy_caps *cmd;
u16 pcaps_size = sizeof(*pcaps);
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
int err;
cmd = &desc.params.get_phy;
cmd = libie_aq_raw(&desc);
if (!pcaps || (report_mode & ~IXGBE_ACI_REPORT_MODE_M))
return -EINVAL;
@ -1091,18 +1091,20 @@ void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,
int ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw,
struct ixgbe_aci_cmd_set_phy_cfg_data *cfg)
{
struct ixgbe_aci_desc desc;
struct ixgbe_aci_cmd_set_phy_cfg *cmd;
struct libie_aq_desc desc;
int err;
if (!cfg)
return -EINVAL;
cmd = libie_aq_raw(&desc);
/* Ensure that only valid bits of cfg->caps can be turned on. */
cfg->caps &= IXGBE_ACI_PHY_ENA_VALID_MASK;
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_phy_cfg);
desc.params.set_phy.lport_num = hw->bus.func;
desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD);
cmd->lport_num = hw->bus.func;
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
err = ixgbe_aci_send_cmd(hw, &desc, cfg, sizeof(*cfg));
if (!err)
@ -1123,9 +1125,9 @@ int ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw,
int ixgbe_aci_set_link_restart_an(struct ixgbe_hw *hw, bool ena_link)
{
struct ixgbe_aci_cmd_restart_an *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
cmd = &desc.params.restart_an;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_restart_an);
@ -1151,9 +1153,9 @@ int ixgbe_aci_set_link_restart_an(struct ixgbe_hw *hw, bool ena_link)
static bool ixgbe_is_media_cage_present(struct ixgbe_hw *hw)
{
struct ixgbe_aci_cmd_get_link_topo *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
cmd = &desc.params.get_link_topo;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo);
@ -1346,7 +1348,7 @@ int ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse,
struct ixgbe_aci_cmd_get_link_status *resp;
struct ixgbe_link_status *li_old, *li;
struct ixgbe_fc_info *hw_fc_info;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
bool tx_pause, rx_pause;
u8 cmd_flags;
int err;
@ -1360,7 +1362,7 @@ int ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse,
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_status);
cmd_flags = (ena_lse) ? IXGBE_ACI_LSE_ENA : IXGBE_ACI_LSE_DIS;
resp = &desc.params.get_link_status;
resp = libie_aq_raw(&desc);
resp->cmd_flags = cpu_to_le16(cmd_flags);
resp->lport_num = hw->bus.func;
@ -1423,9 +1425,9 @@ int ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse,
int ixgbe_aci_set_event_mask(struct ixgbe_hw *hw, u8 port_num, u16 mask)
{
struct ixgbe_aci_cmd_set_event_mask *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
cmd = &desc.params.set_event_mask;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_event_mask);
@ -1496,9 +1498,9 @@ static int ixgbe_start_hw_e610(struct ixgbe_hw *hw)
int ixgbe_aci_set_port_id_led(struct ixgbe_hw *hw, bool orig_mode)
{
struct ixgbe_aci_cmd_set_port_id_led *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
cmd = &desc.params.set_port_id_led;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_port_id_led);
@ -2260,19 +2262,20 @@ int ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw,
struct ixgbe_aci_cmd_get_link_topo *cmd,
u8 *node_part_number, u16 *node_handle)
{
struct ixgbe_aci_desc desc;
struct ixgbe_aci_cmd_get_link_topo *resp;
struct libie_aq_desc desc;
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo);
desc.params.get_link_topo = *cmd;
resp = libie_aq_raw(&desc);
*resp = *cmd;
if (ixgbe_aci_send_cmd(hw, &desc, NULL, 0))
return -EOPNOTSUPP;
if (node_handle)
*node_handle =
le16_to_cpu(desc.params.get_link_topo.addr.handle);
*node_handle = le16_to_cpu(resp->addr.handle);
if (node_part_number)
*node_part_number = desc.params.get_link_topo.node_part_num;
*node_part_number = resp->node_part_num;
return 0;
}
@ -2286,8 +2289,7 @@ int ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw,
*
* Return: the exit code of the operation.
*/
int ixgbe_acquire_nvm(struct ixgbe_hw *hw,
enum ixgbe_aci_res_access_type access)
int ixgbe_acquire_nvm(struct ixgbe_hw *hw, enum libie_aq_res_access_type access)
{
u32 fla;
@ -2296,7 +2298,7 @@ int ixgbe_acquire_nvm(struct ixgbe_hw *hw,
if ((fla & IXGBE_GLNVM_FLA_LOCKED_M) == 0)
return 0;
return ixgbe_acquire_res(hw, IXGBE_NVM_RES_ID, access,
return ixgbe_acquire_res(hw, LIBIE_AQC_RES_ID_NVM, access,
IXGBE_NVM_TIMEOUT);
}
@ -2315,7 +2317,7 @@ void ixgbe_release_nvm(struct ixgbe_hw *hw)
if ((fla & IXGBE_GLNVM_FLA_LOCKED_M) == 0)
return;
ixgbe_release_res(hw, IXGBE_NVM_RES_ID);
ixgbe_release_res(hw, LIBIE_AQC_RES_ID_NVM);
}
/**
@ -2337,12 +2339,12 @@ int ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset,
bool read_shadow_ram)
{
struct ixgbe_aci_cmd_nvm *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
if (offset > IXGBE_ACI_NVM_MAX_OFFSET)
return -EINVAL;
cmd = &desc.params.nvm;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_read);
@ -2372,7 +2374,7 @@ int ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset,
int ixgbe_aci_erase_nvm(struct ixgbe_hw *hw, u16 module_typeid)
{
struct ixgbe_aci_cmd_nvm *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
__le16 len;
int err;
@ -2385,7 +2387,7 @@ int ixgbe_aci_erase_nvm(struct ixgbe_hw *hw, u16 module_typeid)
if (err)
return err;
cmd = &desc.params.nvm;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_erase);
@ -2416,9 +2418,9 @@ int ixgbe_aci_update_nvm(struct ixgbe_hw *hw, u16 module_typeid,
bool last_command, u8 command_flags)
{
struct ixgbe_aci_cmd_nvm *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
cmd = &desc.params.nvm;
cmd = libie_aq_raw(&desc);
/* In offset the highest byte must be zeroed. */
if (offset & 0xFF000000)
@ -2436,7 +2438,7 @@ int ixgbe_aci_update_nvm(struct ixgbe_hw *hw, u16 module_typeid,
cmd->offset_high = FIELD_GET(IXGBE_ACI_NVM_OFFSET_HI_U_MASK, offset);
cmd->length = cpu_to_le16(length);
desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
return ixgbe_aci_send_cmd(hw, &desc, data, length);
}
@ -2467,10 +2469,10 @@ int ixgbe_nvm_write_activate(struct ixgbe_hw *hw, u16 cmd_flags,
u8 *response_flags)
{
struct ixgbe_aci_cmd_nvm *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
s32 err;
cmd = &desc.params.nvm;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc,
ixgbe_aci_opc_nvm_write_activate);
@ -2498,14 +2500,14 @@ int ixgbe_nvm_write_activate(struct ixgbe_hw *hw, u16 cmd_flags,
int ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw)
{
struct ixgbe_aci_cmd_nvm_checksum *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
int err;
err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);
err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ);
if (err)
return err;
cmd = &desc.params.nvm_checksum;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_checksum);
cmd->flags = IXGBE_ACI_NVM_CHECKSUM_VERIFY;
@ -2541,7 +2543,7 @@ static int ixgbe_discover_flash_size(struct ixgbe_hw *hw)
u32 min_size = 0, max_size = IXGBE_ACI_NVM_MAX_OFFSET + 1;
int err;
err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);
err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ);
if (err)
return err;
@ -2552,7 +2554,7 @@ static int ixgbe_discover_flash_size(struct ixgbe_hw *hw)
err = ixgbe_read_flat_nvm(hw, offset, &len, &data, false);
if (err == -EIO &&
hw->aci.last_status == IXGBE_ACI_RC_EINVAL) {
hw->aci.last_status == LIBIE_AQ_RC_EINVAL) {
err = 0;
max_size = offset;
} else if (!err) {
@ -2805,7 +2807,7 @@ static int ixgbe_read_flash_module(struct ixgbe_hw *hw,
if (!start)
return -EINVAL;
err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);
err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ);
if (err)
return err;
@ -3389,7 +3391,7 @@ int ixgbe_get_flash_data(struct ixgbe_hw *hw)
*/
int ixgbe_aci_nvm_update_empr(struct ixgbe_hw *hw)
{
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_update_empr);
@ -3415,15 +3417,15 @@ int ixgbe_nvm_set_pkg_data(struct ixgbe_hw *hw, bool del_pkg_data_flag,
u8 *data, u16 length)
{
struct ixgbe_aci_cmd_nvm_pkg_data *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
if (length != 0 && !data)
return -EINVAL;
cmd = &desc.params.pkg_data;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_pkg_data);
desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
if (del_pkg_data_flag)
cmd->cmd_flags |= IXGBE_ACI_NVM_PKG_DELETE;
@ -3453,17 +3455,17 @@ int ixgbe_nvm_pass_component_tbl(struct ixgbe_hw *hw, u8 *data, u16 length,
u8 *comp_response_code)
{
struct ixgbe_aci_cmd_nvm_pass_comp_tbl *cmd;
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
int err;
if (!data || !comp_response || !comp_response_code)
return -EINVAL;
cmd = &desc.params.pass_comp_tbl;
cmd = libie_aq_raw(&desc);
ixgbe_fill_dflt_direct_cmd_desc(&desc,
ixgbe_aci_opc_nvm_pass_component_tbl);
desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD);
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
cmd->transfer_flag = transfer_flag;
err = ixgbe_aci_send_cmd(hw, &desc, data, length);
@ -3617,7 +3619,7 @@ int ixgbe_read_ee_aci_e610(struct ixgbe_hw *hw, u16 offset, u16 *data)
return err;
}
err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);
err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ);
if (err)
return err;
@ -3650,7 +3652,7 @@ int ixgbe_read_ee_aci_buffer_e610(struct ixgbe_hw *hw, u16 offset,
return err;
}
err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);
err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ);
if (err)
return err;
@ -3690,7 +3692,7 @@ int ixgbe_validate_eeprom_checksum_e610(struct ixgbe_hw *hw, u16 *checksum_val)
if (checksum_val) {
u16 tmp_checksum;
err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);
err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ);
if (err)
return err;

12
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h
View File

@ -6,15 +6,15 @@
#include "ixgbe_type.h"
int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc,
int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct libie_aq_desc *desc,
void *buf, u16 buf_size);
bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw);
int ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e,
bool *pending);
void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode);
int ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,
enum ixgbe_aci_res_access_type access, u32 timeout);
void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res);
void ixgbe_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode);
int ixgbe_acquire_res(struct ixgbe_hw *hw, enum libie_aq_res_id res,
enum libie_aq_res_access_type access, u32 timeout);
void ixgbe_release_res(struct ixgbe_hw *hw, enum libie_aq_res_id res);
int ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size,
u32 *cap_count, enum ixgbe_aci_opc opc);
int ixgbe_discover_dev_caps(struct ixgbe_hw *hw,
@ -62,7 +62,7 @@ int ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw,
struct ixgbe_aci_cmd_get_link_topo *cmd,
u8 *node_part_number, u16 *node_handle);
int ixgbe_acquire_nvm(struct ixgbe_hw *hw,
enum ixgbe_aci_res_access_type access);
enum libie_aq_res_access_type access);
void ixgbe_release_nvm(struct ixgbe_hw *hw);
int ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset,
u16 length, void *data, bool last_command,

4
drivers/net/ethernet/intel/ixgbe/ixgbe_fw_update.c
View File

@ -593,7 +593,7 @@ static int ixgbe_cancel_pending_update(struct ixgbe_adapter *adapter,
"Canceling previous pending update",
component, 0, 0);
err = ixgbe_acquire_nvm(hw, IXGBE_RES_WRITE);
err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_WRITE);
if (err) {
NL_SET_ERR_MSG_MOD(extack,
"Failed to acquire device flash lock");
@ -686,7 +686,7 @@ int ixgbe_flash_pldm_image(struct devlink *devlink,
if (err)
return err;
err = ixgbe_acquire_nvm(hw, IXGBE_RES_WRITE);
err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_WRITE);
if (err) {
NL_SET_ERR_MSG_MOD(extack,
"Failed to acquire device flash lock");

226
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
View File

@ -4,6 +4,8 @@
#ifndef _IXGBE_TYPE_E610_H_
#define _IXGBE_TYPE_E610_H_
#include <linux/net/intel/libie/adminq.h>
#define BYTES_PER_DWORD 4
/* General E610 defines */
@ -135,60 +137,6 @@
/* [ms] timeout of waiting for resource release */
#define IXGBE_ACI_RELEASE_RES_TIMEOUT 10000
/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
#define IXGBE_ACI_LG_BUF 512
/* Flags sub-structure
* |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
* |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
*/
#define IXGBE_ACI_FLAG_DD BIT(0) /* 0x1 */
#define IXGBE_ACI_FLAG_CMP BIT(1) /* 0x2 */
#define IXGBE_ACI_FLAG_ERR BIT(2) /* 0x4 */
#define IXGBE_ACI_FLAG_VFE BIT(3) /* 0x8 */
#define IXGBE_ACI_FLAG_LB BIT(9) /* 0x200 */
#define IXGBE_ACI_FLAG_RD BIT(10) /* 0x400 */
#define IXGBE_ACI_FLAG_VFC BIT(11) /* 0x800 */
#define IXGBE_ACI_FLAG_BUF BIT(12) /* 0x1000 */
#define IXGBE_ACI_FLAG_SI BIT(13) /* 0x2000 */
#define IXGBE_ACI_FLAG_EI BIT(14) /* 0x4000 */
#define IXGBE_ACI_FLAG_FE BIT(15) /* 0x8000 */
/* Admin Command Interface (ACI) error codes */
enum ixgbe_aci_err {
IXGBE_ACI_RC_OK = 0, /* Success */
IXGBE_ACI_RC_EPERM = 1, /* Operation not permitted */
IXGBE_ACI_RC_ENOENT = 2, /* No such element */
IXGBE_ACI_RC_ESRCH = 3, /* Bad opcode */
IXGBE_ACI_RC_EINTR = 4, /* Operation interrupted */
IXGBE_ACI_RC_EIO = 5, /* I/O error */
IXGBE_ACI_RC_ENXIO = 6, /* No such resource */
IXGBE_ACI_RC_E2BIG = 7, /* Arg too long */
IXGBE_ACI_RC_EAGAIN = 8, /* Try again */
IXGBE_ACI_RC_ENOMEM = 9, /* Out of memory */
IXGBE_ACI_RC_EACCES = 10, /* Permission denied */
IXGBE_ACI_RC_EFAULT = 11, /* Bad address */
IXGBE_ACI_RC_EBUSY = 12, /* Device or resource busy */
IXGBE_ACI_RC_EEXIST = 13, /* Object already exists */
IXGBE_ACI_RC_EINVAL = 14, /* Invalid argument */
IXGBE_ACI_RC_ENOTTY = 15, /* Not a typewriter */
IXGBE_ACI_RC_ENOSPC = 16, /* No space left or alloc failure */
IXGBE_ACI_RC_ENOSYS = 17, /* Function not implemented */
IXGBE_ACI_RC_ERANGE = 18, /* Parameter out of range */
IXGBE_ACI_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
IXGBE_ACI_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
IXGBE_ACI_RC_EMODE = 21, /* Op not allowed in current dev mode */
IXGBE_ACI_RC_EFBIG = 22, /* File too big */
IXGBE_ACI_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
IXGBE_ACI_RC_ENOSEC = 24, /* Missing security manifest */
IXGBE_ACI_RC_EBADSIG = 25, /* Bad RSA signature */
IXGBE_ACI_RC_ESVN = 26, /* SVN number prohibits this package */
IXGBE_ACI_RC_EBADMAN = 27, /* Manifest hash mismatch */
IXGBE_ACI_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
IXGBE_ACI_RC_EACCES_BMCU = 29, /* BMC Update in progress */
};
/* Admin Command Interface (ACI) opcodes */
enum ixgbe_aci_opc {
ixgbe_aci_opc_get_ver = 0x0001,
@ -265,33 +213,8 @@ enum ixgbe_aci_opc {
ixgbe_aci_opc_clear_health_status = 0xFF23,
};
/* Get version (direct 0x0001) */
struct ixgbe_aci_cmd_get_ver {
__le32 rom_ver;
__le32 fw_build;
u8 fw_branch;
u8 fw_major;
u8 fw_minor;
u8 fw_patch;
u8 api_branch;
u8 api_major;
u8 api_minor;
u8 api_patch;
};
#define IXGBE_DRV_VER_STR_LEN_E610 32
/* Send driver version (indirect 0x0002) */
struct ixgbe_aci_cmd_driver_ver {
u8 major_ver;
u8 minor_ver;
u8 build_ver;
u8 subbuild_ver;
u8 reserved[4];
__le32 addr_high;
__le32 addr_low;
};
/* Get Expanded Error Code (0x0005, direct) */
struct ixgbe_aci_cmd_get_exp_err {
__le32 reason;
@ -303,98 +226,6 @@ struct ixgbe_aci_cmd_get_exp_err {
/* FW update timeout definitions are in milliseconds */
#define IXGBE_NVM_TIMEOUT 180000
enum ixgbe_aci_res_access_type {
IXGBE_RES_READ = 1,
IXGBE_RES_WRITE
};
enum ixgbe_aci_res_ids {
IXGBE_NVM_RES_ID = 1,
IXGBE_SPD_RES_ID,
IXGBE_CHANGE_LOCK_RES_ID,
IXGBE_GLOBAL_CFG_LOCK_RES_ID
};
/* Request resource ownership (direct 0x0008)
* Release resource ownership (direct 0x0009)
*/
struct ixgbe_aci_cmd_req_res {
__le16 res_id;
__le16 access_type;
/* Upon successful completion, FW writes this value and driver is
* expected to release resource before timeout. This value is provided
* in milliseconds.
*/
__le32 timeout;
#define IXGBE_ACI_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
#define IXGBE_ACI_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
#define IXGBE_ACI_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
#define IXGBE_ACI_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
/* For SDP: pin ID of the SDP */
__le32 res_number;
__le16 status;
#define IXGBE_ACI_RES_GLBL_SUCCESS 0
#define IXGBE_ACI_RES_GLBL_IN_PROG 1
#define IXGBE_ACI_RES_GLBL_DONE 2
u8 reserved[2];
};
/* Get function capabilities (indirect 0x000A)
* Get device capabilities (indirect 0x000B)
*/
struct ixgbe_aci_cmd_list_caps {
u8 cmd_flags;
u8 pf_index;
u8 reserved[2];
__le32 count;
__le32 addr_high;
__le32 addr_low;
};
/* Device/Function buffer entry, repeated per reported capability */
struct ixgbe_aci_cmd_list_caps_elem {
__le16 cap;
#define IXGBE_ACI_CAPS_VALID_FUNCTIONS 0x0005
#define IXGBE_ACI_MAX_VALID_FUNCTIONS 0x8
#define IXGBE_ACI_CAPS_SRIOV 0x0012
#define IXGBE_ACI_CAPS_VF 0x0013
#define IXGBE_ACI_CAPS_VMDQ 0x0014
#define IXGBE_ACI_CAPS_VSI 0x0017
#define IXGBE_ACI_CAPS_DCB 0x0018
#define IXGBE_ACI_CAPS_RSS 0x0040
#define IXGBE_ACI_CAPS_RXQS 0x0041
#define IXGBE_ACI_CAPS_TXQS 0x0042
#define IXGBE_ACI_CAPS_MSIX 0x0043
#define IXGBE_ACI_CAPS_FD 0x0045
#define IXGBE_ACI_CAPS_1588 0x0046
#define IXGBE_ACI_CAPS_MAX_MTU 0x0047
#define IXGBE_ACI_CAPS_NVM_VER 0x0048
#define IXGBE_ACI_CAPS_PENDING_NVM_VER 0x0049
#define IXGBE_ACI_CAPS_OROM_VER 0x004A
#define IXGBE_ACI_CAPS_PENDING_OROM_VER 0x004B
#define IXGBE_ACI_CAPS_PENDING_NET_VER 0x004D
#define IXGBE_ACI_CAPS_INLINE_IPSEC 0x0070
#define IXGBE_ACI_CAPS_NUM_ENABLED_PORTS 0x0072
#define IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE 0x0076
#define IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
#define IXGBE_ACI_CAPS_NVM_MGMT 0x0080
#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0 0x0081
#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1 0x0082
#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2 0x0083
#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3 0x0084
u8 major_ver;
u8 minor_ver;
/* Number of resources described by this capability */
__le32 number;
/* Only meaningful for some types of resources */
__le32 logical_id;
/* Only meaningful for some types of resources */
__le32 phys_id;
__le64 rsvd1;
__le64 rsvd2;
};
/* Disable RXEN (direct 0x000C) */
struct ixgbe_aci_cmd_disable_rxen {
u8 lport_num;
@ -960,55 +791,6 @@ struct ixgbe_aci_cmd_nvm_comp_tbl {
u8 cvs[]; /* Component Version String */
} __packed;
/**
* struct ixgbe_aci_desc - Admin Command (AC) descriptor
* @flags: IXGBE_ACI_FLAG_* flags
* @opcode: Admin command opcode
* @datalen: length in bytes of indirect/external data buffer
* @retval: return value from firmware
* @cookie_high: opaque data high-half
* @cookie_low: opaque data low-half
* @params: command-specific parameters
*
* Descriptor format for commands the driver posts via the
* Admin Command Interface (ACI).
* The firmware writes back onto the command descriptor and returns
* the result of the command. Asynchronous events that are not an immediate
* result of the command are written to the Admin Command Interface (ACI) using
* the same descriptor format. Descriptors are in little-endian notation with
* 32-bit words.
*/
struct ixgbe_aci_desc {
__le16 flags;
__le16 opcode;
__le16 datalen;
__le16 retval;
__le32 cookie_high;
__le32 cookie_low;
union {
u8 raw[16];
struct ixgbe_aci_cmd_get_ver get_ver;
struct ixgbe_aci_cmd_driver_ver driver_ver;
struct ixgbe_aci_cmd_get_exp_err exp_err;
struct ixgbe_aci_cmd_req_res res_owner;
struct ixgbe_aci_cmd_list_caps get_cap;
struct ixgbe_aci_cmd_disable_rxen disable_rxen;
struct ixgbe_aci_cmd_get_phy_caps get_phy;
struct ixgbe_aci_cmd_set_phy_cfg set_phy;
struct ixgbe_aci_cmd_restart_an restart_an;
struct ixgbe_aci_cmd_get_link_status get_link_status;
struct ixgbe_aci_cmd_set_event_mask set_event_mask;
struct ixgbe_aci_cmd_set_port_id_led set_port_id_led;
struct ixgbe_aci_cmd_get_link_topo get_link_topo;
struct ixgbe_aci_cmd_get_link_topo_pin get_link_topo_pin;
struct ixgbe_aci_cmd_sff_eeprom read_write_sff_param;
struct ixgbe_aci_cmd_nvm nvm;
struct ixgbe_aci_cmd_nvm_checksum nvm_checksum;
struct ixgbe_aci_cmd_nvm_pkg_data pkg_data;
struct ixgbe_aci_cmd_nvm_pass_comp_tbl pass_comp_tbl;
} params;
};
/* E610-specific adapter context structures */
struct ixgbe_link_status {
@ -1172,7 +954,7 @@ struct ixgbe_hw_dev_caps {
/* ACI event information */
struct ixgbe_aci_event {
struct ixgbe_aci_desc desc;
struct libie_aq_desc desc;
u8 *msg_buf;
u16 msg_len;
u16 buf_len;
@ -1180,7 +962,7 @@ struct ixgbe_aci_event {
struct ixgbe_aci_info {
struct mutex lock; /* admin command interface lock */
enum ixgbe_aci_err last_status; /* last status of sent admin command */
enum libie_aq_err last_status; /* last status of sent admin command */
};
enum ixgbe_bank_select {

6
drivers/net/ethernet/intel/libie/Kconfig
View File

@ -8,3 +8,9 @@ config LIBIE
libie (Intel Ethernet library) is a common library built on top of
libeth and containing vendor-specific routines shared between several
Intel Ethernet drivers.
config LIBIE_ADMINQ
tristate
help
Helper functions used by Intel Ethernet drivers for administration
queue command interface (aka adminq).

4
drivers/net/ethernet/intel/libie/Makefile
View File

@ -4,3 +4,7 @@
obj-$(CONFIG_LIBIE) += libie.o
libie-y := rx.o
obj-$(CONFIG_LIBIE_ADMINQ) += libie_adminq.o
libie_adminq-y := adminq.o

52
drivers/net/ethernet/intel/libie/adminq.c Normal file
View File

@ -0,0 +1,52 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (C) 2025 Intel Corporation */
#include <linux/module.h>
#include <linux/net/intel/libie/adminq.h>
static const char * const libie_aq_str_arr[] = {
#define LIBIE_AQ_STR(x) \
[LIBIE_AQ_RC_##x] = "LIBIE_AQ_RC" #x
LIBIE_AQ_STR(OK),
LIBIE_AQ_STR(EPERM),
LIBIE_AQ_STR(ENOENT),
LIBIE_AQ_STR(ESRCH),
LIBIE_AQ_STR(EIO),
LIBIE_AQ_STR(EAGAIN),
LIBIE_AQ_STR(ENOMEM),
LIBIE_AQ_STR(EACCES),
LIBIE_AQ_STR(EBUSY),
LIBIE_AQ_STR(EEXIST),
LIBIE_AQ_STR(EINVAL),
LIBIE_AQ_STR(ENOSPC),
LIBIE_AQ_STR(ENOSYS),
LIBIE_AQ_STR(EMODE),
LIBIE_AQ_STR(ENOSEC),
LIBIE_AQ_STR(EBADSIG),
LIBIE_AQ_STR(ESVN),
LIBIE_AQ_STR(EBADMAN),
LIBIE_AQ_STR(EBADBUF),
#undef LIBIE_AQ_STR
"LIBIE_AQ_RC_UNKNOWN",
};
#define __LIBIE_AQ_STR_NUM (ARRAY_SIZE(libie_aq_str_arr) - 1)
/**
* libie_aq_str - get error string based on aq error
* @err: admin queue error type
*
* Return: error string for passed error code
*/
const char *libie_aq_str(enum libie_aq_err err)
{
if (err >= ARRAY_SIZE(libie_aq_str_arr) ||
!libie_aq_str_arr[err])
err = __LIBIE_AQ_STR_NUM;
return libie_aq_str_arr[err];
}
EXPORT_SYMBOL_NS_GPL(libie_aq_str, "LIBIE_ADMINQ");
MODULE_DESCRIPTION("Intel(R) Ethernet common library - adminq helpers");
MODULE_LICENSE("GPL");

308
include/linux/net/intel/libie/adminq.h Normal file
View File

@ -0,0 +1,308 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (C) 2025 Intel Corporation */
#ifndef __LIBIE_ADMINQ_H
#define __LIBIE_ADMINQ_H
#include <linux/build_bug.h>
#include <linux/types.h>
#define LIBIE_CHECK_STRUCT_LEN(n, X) \
static_assert((n) == sizeof(struct X))
/**
* struct libie_aqc_generic - Generic structure used in adminq communication
* @param0: generic parameter high 32bit
* @param1: generic parameter lower 32bit
* @addr_high: generic address high 32bit
* @addr_low: generic address lower 32bit
*/
struct libie_aqc_generic {
__le32 param0;
__le32 param1;
__le32 addr_high;
__le32 addr_low;
};
LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_generic);
/**
* struct libie_aqc_get_ver - Used in command get version (direct 0x0001)
* @rom_ver: rom version
* @fw_build: number coressponding to firmware build
* @fw_branch: branch identifier of firmware version
* @fw_major: major number of firmware version
* @fw_minor: minor number of firmware version
* @fw_patch: patch of firmware version
* @api_branch: brancch identifier of API version
* @api_major: major number of API version
* @api_minor: minor number of API version
* @api_patch: patch of API version
*/
struct libie_aqc_get_ver {
__le32 rom_ver;
__le32 fw_build;
u8 fw_branch;
u8 fw_major;
u8 fw_minor;
u8 fw_patch;
u8 api_branch;
u8 api_major;
u8 api_minor;
u8 api_patch;
};
LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_get_ver);
/**
* struct libie_aqc_driver_ver - Used in command send driver version
* (indirect 0x0002)
* @major_ver: driver major version
* @minor_ver: driver minor version
* @build_ver: driver build version
* @subbuild_ver: driver subbuild version
* @reserved: for feature use
* @addr_high: high part of response address buff
* @addr_low: low part of response address buff
*/
struct libie_aqc_driver_ver {
u8 major_ver;
u8 minor_ver;
u8 build_ver;
u8 subbuild_ver;
u8 reserved[4];
__le32 addr_high;
__le32 addr_low;
};
LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_driver_ver);
enum libie_aq_res_id {
LIBIE_AQC_RES_ID_NVM = 1,
LIBIE_AQC_RES_ID_SDP = 2,
LIBIE_AQC_RES_ID_CHNG_LOCK = 3,
LIBIE_AQC_RES_ID_GLBL_LOCK = 4,
};
enum libie_aq_res_access_type {
LIBIE_AQC_RES_ACCESS_READ = 1,
LIBIE_AQC_RES_ACCESS_WRITE = 2,
};
#define LIBIE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
#define LIBIE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
#define LIBIE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
#define LIBIE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
#define LIBIE_AQ_RES_GLBL_SUCCESS 0
#define LIBIE_AQ_RES_GLBL_IN_PROG 1
#define LIBIE_AQ_RES_GLBL_DONE 2
/**
* struct libie_aqc_req_res - Request resource ownership
* @res_id: resource ID (look at enum definition above)
* @access_type: read or write (enum definition above)
* @timeout: Upon successful completion, FW writes this value and driver is
* expected to release resource before timeout. This value is provided in
* milliseconds.
* @res_number: for SDP, this is the pin ID of the SDP
* @status: status only used for LIBIE_AQC_RES_ID_GLBL_LOCK, for others reserved
* @reserved: reserved for future use
*
* Used in commands:
* request resource ownership (direct 0x0008)
* request resource ownership (direct 0x0009)
*/
struct libie_aqc_req_res {
__le16 res_id;
__le16 access_type;
__le32 timeout;
__le32 res_number;
__le16 status;
u8 reserved[2];
};
LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_req_res);
/**
* struct libie_aqc_list_caps - Getting capabilities
* @cmd_flags: command flags
* @pf_index: index of PF to get caps from
* @reserved: reserved for future use
* @count: number of capabilities records
* @addr_high: high part of response address buff
* @addr_low: low part of response address buff
*
* Used in commands:
* get function capabilities (indirect 0x000A)
* get device capabilities (indirect 0x000B)
*/
struct libie_aqc_list_caps {
u8 cmd_flags;
u8 pf_index;
u8 reserved[2];
__le32 count;
__le32 addr_high;
__le32 addr_low;
};
LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_list_caps);
/* Device/Function buffer entry, repeated per reported capability */
#define LIBIE_AQC_CAPS_SWITCH_MODE 0x0001
#define LIBIE_AQC_CAPS_MNG_MODE 0x0002
#define LIBIE_AQC_CAPS_NPAR_ACTIVE 0x0003
#define LIBIE_AQC_CAPS_OS2BMC_CAP 0x0004
#define LIBIE_AQC_CAPS_VALID_FUNCTIONS 0x0005
#define LIBIE_AQC_MAX_VALID_FUNCTIONS 0x8
#define LIBIE_AQC_CAPS_SRIOV 0x0012
#define LIBIE_AQC_CAPS_VF 0x0013
#define LIBIE_AQC_CAPS_VMDQ 0x0014
#define LIBIE_AQC_CAPS_8021QBG 0x0015
#define LIBIE_AQC_CAPS_8021QBR 0x0016
#define LIBIE_AQC_CAPS_VSI 0x0017
#define LIBIE_AQC_CAPS_DCB 0x0018
#define LIBIE_AQC_CAPS_FCOE 0x0021
#define LIBIE_AQC_CAPS_ISCSI 0x0022
#define LIBIE_AQC_CAPS_RSS 0x0040
#define LIBIE_AQC_CAPS_RXQS 0x0041
#define LIBIE_AQC_CAPS_TXQS 0x0042
#define LIBIE_AQC_CAPS_MSIX 0x0043
#define LIBIE_AQC_CAPS_VF_MSIX 0x0044
#define LIBIE_AQC_CAPS_FD 0x0045
#define LIBIE_AQC_CAPS_1588 0x0046
#define LIBIE_AQC_CAPS_MAX_MTU 0x0047
#define LIBIE_AQC_CAPS_NVM_VER 0x0048
#define LIBIE_AQC_CAPS_PENDING_NVM_VER 0x0049
#define LIBIE_AQC_CAPS_OROM_VER 0x004A
#define LIBIE_AQC_CAPS_PENDING_OROM_VER 0x004B
#define LIBIE_AQC_CAPS_NET_VER 0x004C
#define LIBIE_AQC_CAPS_PENDING_NET_VER 0x004D
#define LIBIE_AQC_CAPS_RDMA 0x0051
#define LIBIE_AQC_CAPS_LED 0x0061
#define LIBIE_AQC_CAPS_SDP 0x0062
#define LIBIE_AQC_CAPS_MDIO 0x0063
#define LIBIE_AQC_CAPS_WSR_PROT 0x0064
#define LIBIE_AQC_CAPS_SENSOR_READING 0x0067
#define LIBIE_AQC_INLINE_IPSEC 0x0070
#define LIBIE_AQC_CAPS_NUM_ENABLED_PORTS 0x0072
#define LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
#define LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
#define LIBIE_AQC_CAPS_NVM_MGMT 0x0080
#define LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081
#define LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082
#define LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083
#define LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084
#define LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085
#define LIBIE_AQC_CAPS_NAC_TOPOLOGY 0x0087
#define LIBIE_AQC_CAPS_FW_LAG_SUPPORT 0x0092
#define LIBIE_AQC_BIT_ROCEV2_LAG 0x01
#define LIBIE_AQC_BIT_SRIOV_LAG 0x02
#define LIBIE_AQC_CAPS_FLEX10 0x00F1
#define LIBIE_AQC_CAPS_CEM 0x00F2
/**
* struct libie_aqc_list_caps_elem - Getting list of caps elements
* @cap: one from the defines list above
* @major_ver: major version
* @minor_ver: minor version
* @number: number of resources described by this capability
* @logical_id: logical ID, only meaningful for some types of resources
* @phys_id: physical ID, only meaningful for some types of resources
* @rsvd1: reserved for future use
* @rsvd2: reserved for future use
*/
struct libie_aqc_list_caps_elem {
__le16 cap;
u8 major_ver;
u8 minor_ver;
__le32 number;
__le32 logical_id;
__le32 phys_id;
__le64 rsvd1;
__le64 rsvd2;
};
LIBIE_CHECK_STRUCT_LEN(32, libie_aqc_list_caps_elem);
/**
* struct libie_aq_desc - Admin Queue (AQ) descriptor
* @flags: LIBIE_AQ_FLAG_* flags
* @opcode: AQ command opcode
* @datalen: length in bytes of indirect/external data buffer
* @retval: return value from firmware
* @cookie_high: opaque data high-half
* @cookie_low: opaque data low-half
* @params: command-specific parameters
*
* Descriptor format for commands the driver posts on the Admin Transmit Queue
* (ATQ). The firmware writes back onto the command descriptor and returns
* the result of the command. Asynchronous events that are not an immediate
* result of the command are written to the Admin Receive Queue (ARQ) using
* the same descriptor format. Descriptors are in little-endian notation with
* 32-bit words.
*/
struct libie_aq_desc {
__le16 flags;
__le16 opcode;
__le16 datalen;
__le16 retval;
__le32 cookie_high;
__le32 cookie_low;
union {
u8 raw[16];
struct libie_aqc_generic generic;
struct libie_aqc_get_ver get_ver;
struct libie_aqc_driver_ver driver_ver;
struct libie_aqc_req_res res_owner;
struct libie_aqc_list_caps get_cap;
} params;
};
LIBIE_CHECK_STRUCT_LEN(32, libie_aq_desc);
/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
#define LIBIE_AQ_LG_BUF 512
/* Flags sub-structure
* |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
* |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
*/
#define LIBIE_AQ_FLAG_DD BIT(0) /* 0x1 */
#define LIBIE_AQ_FLAG_CMP BIT(1) /* 0x2 */
#define LIBIE_AQ_FLAG_ERR BIT(2) /* 0x4 */
#define LIBIE_AQ_FLAG_VFE BIT(3) /* 0x8 */
#define LIBIE_AQ_FLAG_LB BIT(9) /* 0x200 */
#define LIBIE_AQ_FLAG_RD BIT(10) /* 0x400 */
#define LIBIE_AQ_FLAG_VFC BIT(11) /* 0x800 */
#define LIBIE_AQ_FLAG_BUF BIT(12) /* 0x1000 */
#define LIBIE_AQ_FLAG_SI BIT(13) /* 0x2000 */
#define LIBIE_AQ_FLAG_EI BIT(14) /* 0x4000 */
#define LIBIE_AQ_FLAG_FE BIT(15) /* 0x8000 */
/* error codes */
enum libie_aq_err {
LIBIE_AQ_RC_OK = 0, /* Success */
LIBIE_AQ_RC_EPERM = 1, /* Operation not permitted */
LIBIE_AQ_RC_ENOENT = 2, /* No such element */
LIBIE_AQ_RC_ESRCH = 3, /* Bad opcode */
LIBIE_AQ_RC_EIO = 5, /* I/O error */
LIBIE_AQ_RC_EAGAIN = 8, /* Try again */
LIBIE_AQ_RC_ENOMEM = 9, /* Out of memory */
LIBIE_AQ_RC_EACCES = 10, /* Permission denied */
LIBIE_AQ_RC_EBUSY = 12, /* Device or resource busy */
LIBIE_AQ_RC_EEXIST = 13, /* Object already exists */
LIBIE_AQ_RC_EINVAL = 14, /* Invalid argument */
LIBIE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
LIBIE_AQ_RC_ENOSYS = 17, /* Function not implemented */
LIBIE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
LIBIE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
LIBIE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
LIBIE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
LIBIE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
LIBIE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
};
static inline void *libie_aq_raw(struct libie_aq_desc *desc)
{
return &desc->params.raw;
}
const char *libie_aq_str(enum libie_aq_err err);
#endif /* __LIBIE_ADMINQ_H */