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arm64: dts: qcom: glymur: Add PCIe port compatibles and ports

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Centrally define the endpoints to let device DTs that describe PCIe
devices and/or M.2 connectors refer to them without error-prone
duplication.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260716-topic-smb2370_port2-v1-2-83d02b2ba4b0@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Konrad Dybcio 2026-07-16 19:33:43 +02:00 committed by Bjorn Andersson
parent f922f586c6
commit e9d928da6f
1 changed files with 24 additions and 0 deletions
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24
arch/arm64/boot/dts/qcom/glymur.dtsi
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@ -2946,6 +2946,7 @@ opp-32000000-4 {
pcie4_port0: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@ -2954,6 +2955,11 @@ pcie4_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
port {
pcie4_port0_ep: endpoint {
};
};
};
};
@ -3212,6 +3218,7 @@ opp-128000000-5 {
pcie5_port0: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@ -3220,6 +3227,11 @@ pcie5_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
port {
pcie5_port0_ep: endpoint {
};
};
};
};
@ -3422,6 +3434,7 @@ opp-32000000-4 {
pcie6_port0: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@ -3430,6 +3443,11 @@ pcie6_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
port {
pcie6_port0_ep: endpoint {
};
};
};
};
@ -3688,6 +3706,7 @@ opp-128000000-5 {
pcie3b_port0: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@ -3696,6 +3715,11 @@ pcie3b_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
port {
pcie3b_port0_ep: endpoint {
};
};
};
};