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perf/x86/intel: Update event constraints and cache_extra_regsfor MTL

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Update perf hard-coded event constraints and cache_extra_regs[] for
Meteor Lake according to the latest MTL perfmon events (V1.21).

MTL P-core (redwoodcove) inherits same perf events list from previous
generation (Goldencove), but the E-core (Crestmont) brings some
difference on the perf event list comparing with Gracemont. So apply
the changes for Crestmont core.

MTL perfmon events:
https://github.com/intel/perfmon/blob/main/MTL/events/meteorlake_redwoodcove_core.json
https://github.com/intel/perfmon/blob/main/MTL/events/meteorlake_crestmont_core.json

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-6-dapeng1.mi@linux.intel.com
This commit is contained in:
Dapeng Mi 2026-05-15 14:11:37 +08:00 committed by Peter Zijlstra
parent 4ef863352b
commit e99fb45436
3 changed files with 34 additions and 2 deletions
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27
arch/x86/events/intel/core.c
View File

@ -2494,6 +2494,21 @@ static __initconst const u64 grt_hw_cache_extra_regs
},
};
static __initconst const u64 cmt_hw_cache_extra_regs
[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX]
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
[C(LL)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
[C(RESULT_MISS)] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
[C(RESULT_MISS)] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
},
},
};
static __initconst const u64 arw_hw_cache_extra_regs
[PERF_COUNT_HW_CACHE_MAX]
@ -7677,6 +7692,15 @@ static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
intel_pmu_ref_cycles_ext();
}
static __always_inline void intel_pmu_init_cmt(struct pmu *pmu)
{
intel_pmu_init_grt(pmu);
memcpy(hybrid_var(pmu, hw_cache_extra_regs),
cmt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
hybrid(pmu, pebs_constraints) = intel_cmt_pebs_event_constraints;
hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
}
static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
{
intel_pmu_init_glc(pmu);
@ -8489,8 +8513,7 @@ __init int intel_pmu_init(void)
/* Initialize Atom core specific PerfMon capabilities.*/
pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
intel_pmu_init_grt(&pmu->pmu);
pmu->extra_regs = intel_cmt_extra_regs;
intel_pmu_init_cmt(&pmu->pmu);
intel_pmu_pebs_data_source_mtl();
pr_cont("Meteorlake Hybrid events, ");

7
arch/x86/events/intel/ds.c
View File

@ -1296,6 +1296,13 @@ struct event_constraint intel_grt_pebs_event_constraints[] = {
EVENT_CONSTRAINT_END
};
struct event_constraint intel_cmt_pebs_event_constraints[] = {
/* Allow all events as PEBS with no flags */
INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
EVENT_CONSTRAINT_END
};
struct event_constraint intel_arw_pebs_event_constraints[] = {
/* Allow all events as PEBS with no flags */
INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff),

2
arch/x86/events/perf_event.h
View File

@ -1710,6 +1710,8 @@ extern struct event_constraint intel_glp_pebs_event_constraints[];
extern struct event_constraint intel_grt_pebs_event_constraints[];
extern struct event_constraint intel_cmt_pebs_event_constraints[];
extern struct event_constraint intel_arw_pebs_event_constraints[];
extern struct event_constraint intel_nehalem_pebs_event_constraints[];