From b99b8832e4c90be199647bdd03a96d08b2000dce Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 24 May 2017 11:06:16 +0800 Subject: [PATCH 1/9] ARM: sun8i: a83t: Add device node and pinmux setting for RSB controller The A83T has an RSB controller for talking to the PMIC and audio codec. Add a device node for it. Since there is only one usable pinmux setting, for it, add that as well. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index d9b4372dbdf3..61304761e8f6 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -47,6 +47,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -379,6 +380,28 @@ r_pio: pinctrl@1f02c00 { #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; + + r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + drive-strength = <20>; + bias-pull-up; + }; + }; + + r_rsb: rsb@1f03400 { + compatible = "allwinner,sun8i-a83t-rsb", + "allwinner,sun8i-a23-rsb"; + reg = <0x01f03400 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_APB0_RSB>; + clock-frequency = <3000000>; + resets = <&r_ccu RST_APB0_RSB>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; }; }; From 31f0491da62061b90a1069cbec63b9e13cd9ee7f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 24 May 2017 13:40:15 +0800 Subject: [PATCH 2/9] ARM: sun8i: a83t: cubietruck-plus: Enable PMIC part of AXP818 PMIC The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies in one package sharing the serial bus (I2C/RSB) pins. One die is the actual PMIC. The other is an AC100 codec / RTC combo chip. This patch enables the RSB controller and adds a device node for the PMIC die to the Cubietruck Plus device tree. Since the AXP813 and AXP818 are virtually identical, this patch uses the compatible string for the former as a fallback. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index 163ddf8868b5..d88a22ac6222 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -129,6 +129,17 @@ &mmc2 { status = "okay"; }; +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp818", "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &spdif { status = "okay"; }; From 0c62fb093e4093de1bc7432c4ffc2dca44d73c51 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 24 May 2017 13:37:00 +0800 Subject: [PATCH 3/9] ARM: sun8i: a83t: cubietruck-plus: Enable AC100 combo chip in AXP818 PMIC The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies in one package sharing the serial bus (I2C/RSB) pins. One die is the actual PMIC. The other is an AC100 codec / RTC combo chip. This patch adds the device nodes for the AC100 chip to the Cubietruck Plus device tree. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- .../boot/dts/sun8i-a83t-cubietruck-plus.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index d88a22ac6222..f583e5b9a1c8 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -138,6 +138,30 @@ axp81x: pmic@3a3 { interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; }; &spdif { From 29067930e74d3fb3e3cffaa999642eb526dd4d4e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 20 Jul 2017 16:01:02 +0800 Subject: [PATCH 4/9] ARM: sun8i: a83t: h8homlet-v2: Enable PMIC part of AXP818 PMIC The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies in one package sharing the serial bus (I2C/RSB) pins. One die is the actual PMIC. The other is an AC100 codec / RTC combo chip. This patch enables the RSB controller and adds a device node for the PMIC die to the h8homlet-v2 device tree. Since the AXP813 and AXP818 are virtually identical, this patch uses the compatible string for the former as a fallback. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- .../arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 7afbaa4eea8d..7e92baa63f1c 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -78,6 +78,17 @@ &mmc2 { status = "okay"; }; +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp818", "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From 5bcfff2cc392f72d488633b1ede4c6d8fae22520 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 20 Jul 2017 16:02:25 +0800 Subject: [PATCH 5/9] ARM: sun8i: a83t: h8homlet-v2: Enable AC100 combo chip in AXP818 PMIC The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies in one package sharing the serial bus (I2C/RSB) pins. One die is the actual PMIC. The other is an AC100 codec / RTC combo chip. This patch adds the device nodes for the AC100 chip to the h8homlet-v2 device tree. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 7e92baa63f1c..e0055180d29f 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -87,6 +87,30 @@ axp81x: pmic@3a3 { interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; }; &uart0 { From 05a6a90df8fbd758844ac69e528f5528910b9552 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Aug 2017 16:14:08 +0800 Subject: [PATCH 6/9] ARM: sun8i: a83t: Add USB PHY and host device nodes The A83T has 3 USB PHYs, 1 for USB OTG, 1 for standard USB 2.0, 1 for USB HSIC. EHCI0/OHCI0 are the standard USB host pair, while EHCI1 is the host controller for HSIC. OTG is not added yet. Signed-off-by: Chen-Yu Tsai Tested-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 62 +++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 61304761e8f6..6039f1ea6810 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -242,6 +242,68 @@ mmc2: mmc@1c11000 { #size-cells = <0>; }; + usbphy: phy@1c19400 { + compatible = "allwinner,sun8i-a83t-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x14>, + <0x01c1b800 0x14>; + reg-names = "phy_ctrl", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_HSIC>, + <&ccu CLK_USB_HSIC_12M>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb2_hsic_12M"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_HSIC>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@1c1a000 { + compatible = "allwinner,sun8i-a83t-ehci", + "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI0>; + resets = <&ccu RST_BUS_EHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@1c1a400 { + compatible = "allwinner,sun8i-a83t-ohci", + "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@1c1b000 { + compatible = "allwinner,sun8i-a83t-ehci", + "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI1>; + resets = <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-a83t-ccu"; reg = <0x01c20000 0x400>; From 25ac8b9bffb4855423c29262e83c38ef119944f4 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Aug 2017 16:14:09 +0800 Subject: [PATCH 7/9] ARM: sun8i: a83t: Add device node for USB OTG controller The USB OTG controller found on the A83T is compatible with the one found on the A33. Add a device node for it. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a83t.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 6039f1ea6810..f996bd343e50 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -242,6 +242,20 @@ mmc2: mmc@1c11000 { #size-cells = <0>; }; + usb_otg: usb@01c19000 { + compatible = "allwinner,sun8i-a83t-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + usbphy: phy@1c19400 { compatible = "allwinner,sun8i-a83t-usb-phy"; reg = <0x01c19400 0x10>, From 9f851d4ee69d53565c1953dedbdd4ebe9acaff49 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Aug 2017 16:14:10 +0800 Subject: [PATCH 8/9] ARM: sun8i: a83t: cubietruck-plus: Enable onboard USB peripherals The Cubietruck-plus has a GL830 USB-to-SATA bridge connected to EHCI0, and a USB3503 HSIC USB 2.0 hub connected to EHCI1. The USB3503's I2C control interface is not connected. This patch enables both EHCI controllers, adds a device node for the USB hub, and includes sunxi-common-regulators.dtsi for the VBUS regulators. The existing reg_vcc3v3 is dropped as it is also available in the set of common regulators. Other unused regulators are disabled. Signed-off-by: Chen-Yu Tsai --- .../boot/dts/sun8i-a83t-cubietruck-plus.dts | 49 +++++++++++++++++-- 1 file changed, 44 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index f583e5b9a1c8..716a205c6dbb 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -44,6 +44,7 @@ /dts-v1/; #include "sun8i-a83t.dtsi" +#include "sunxi-common-regulators.dtsi" #include @@ -83,11 +84,15 @@ green { }; }; - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + usb-hub { + /* I2C is not connected */ + compatible = "smsc,usb3503"; + initial-mode = <1>; /* initialize in HUB mode */ + disabled-ports = <1>; + intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */ + connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + refclk-frequency = <19200000>; }; sound { @@ -109,6 +114,16 @@ spdif_out: spdif-out { }; }; +&ehci0 { + /* GL830 USB-to-SATA bridge here */ + status = "okay"; +}; + +&ehci1 { + /* USB3503 HSIC USB 2.0 hub here */ + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -164,6 +179,24 @@ ac100_rtc: rtc { }; }; +®_usb1_vbus { + gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + status = "okay"; +}; + +®_vcc3v0 { + status = "disabled"; +}; + +®_vcc5v0 { + status = "disabled"; +}; + &spdif { status = "okay"; }; @@ -173,3 +206,9 @@ &uart0 { pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; From 75ce73fdadf6944d6948f45b34cbfd7aa01190cc Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Aug 2017 16:14:11 +0800 Subject: [PATCH 9/9] ARM: sun8i: a83t: h8homlet-v2: Enable USB ports The h8homlet board has the A83T's standard USB 1.1/2.0 host pair routed to a USB host port on the board. The other USB host port is routed to USB OTG controller. Signed-off-by: Chen-Yu Tsai --- .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index e0055180d29f..1f0d60afb25b 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -58,6 +58,10 @@ chosen { }; }; +&ehci0 { + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -78,6 +82,20 @@ &mmc2 { status = "okay"; }; +&ohci0 { + status = "okay"; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + status = "okay"; +}; + &r_rsb { status = "okay"; @@ -118,3 +136,14 @@ &uart0 { pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; + +&usbphy { + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +};