From e97157ebab19151728be59f8d0da9036104cc79e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 21 Jul 2026 13:43:19 +0200 Subject: [PATCH] drm/amdgpu/gfx7: Clean up gfx ring during reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clear the WPTR and RPTR at ring initialization. Additionally clear the ring contents during reset. After a reset, the ring contents could be "dirty" and contain packets emitted before the reset. and thus need to be cleared to prevent the command processor from executing packets left over in the ring from before the reset. Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index dac520eb0553..7a3b7272d093 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2547,8 +2547,12 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) WREG32(mmSCRATCH_ADDR, 0); /* ring 0 - compute and gfx */ - /* Set ring buffer size */ ring = &adev->gfx.gfx_ring[0]; + *ring->wptr_cpu_addr = 0; + *ring->rptr_cpu_addr = 0; + amdgpu_ring_clear_ring(ring); + + /* Set ring buffer size */ rb_bufsz = order_base_2(ring->ring_size / 8); tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; #ifdef __BIG_ENDIAN @@ -2560,6 +2564,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); + WREG32(mmCP_RB0_RPTR, lower_32_bits(ring->wptr)); /* set the wb address whether it's enabled or not */ rptr_addr = ring->rptr_gpu_addr;