github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-28 09:04:39 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/i915/dsc: Switch to using intel_dsc_line_slice_count()

Browse Source 
By now all the places are updated to track the DSC slice configuration
in intel_crtc_state::dsc.slice_config, so calculate the slices-per-line
value using that config, instead of using
intel_crtc_state::dsc.slice_count caching the same value and remove
the cached slice_count.

v2: Rebase on latest drm-tip, converting another user of dsc.slice_count
    in intel_vdsc_min_cdclk().

Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com> # v1
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260114162232.92731-7-imre.deak@intel.com
This commit is contained in:
Imre Deak 2026-01-14 18:22:23 +02:00
parent fd1e610ca2
commit e941eb1078
4 changed files with 12 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/i915/display/intel_bios.c
View File

@ -3597,14 +3597,12 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
crtc_state->dsc.slice_config.slices_per_stream = 1;
}
crtc_state->dsc.slice_count = intel_dsc_line_slice_count(&crtc_state->dsc.slice_config);
if (crtc_state->hw.adjusted_mode.crtc_hdisplay %
crtc_state->dsc.slice_count != 0)
intel_dsc_line_slice_count(&crtc_state->dsc.slice_config) != 0)
drm_dbg_kms(display->drm,
"VBT: DSC hdisplay %d not divisible by slice count %d\n",
crtc_state->hw.adjusted_mode.crtc_hdisplay,
crtc_state->dsc.slice_count);
intel_dsc_line_slice_count(&crtc_state->dsc.slice_config));
/*
* The VBT rc_buffer_block_size and rc_buffer_size definitions

1
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -1339,7 +1339,6 @@ struct intel_crtc_state {
} slice_config;
/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
u16 compressed_bpp_x16;
u8 slice_count;
struct drm_dsc_config config;
} dsc;

11
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -2032,12 +2032,14 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
} else {
unsigned long bw_overhead_flags =
pipe_config->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
int line_slice_count =
intel_dsc_line_slice_count(&pipe_config->dsc.slice_config);
if (!is_bw_sufficient_for_dsc_config(intel_dp,
link_rate, lane_count,
adjusted_mode->crtc_clock,
adjusted_mode->hdisplay,
pipe_config->dsc.slice_count,
line_slice_count,
dsc_bpp_x16,
bw_overhead_flags))
continue;
@ -2428,11 +2430,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->dsc.slice_config.pipes_per_line /
pipe_config->dsc.slice_config.streams_per_pipe;
pipe_config->dsc.slice_count =
intel_dsc_line_slice_count(&pipe_config->dsc.slice_config);
drm_WARN_ON(display->drm,
pipe_config->dsc.slice_count != slices_per_line);
intel_dsc_line_slice_count(&pipe_config->dsc.slice_config) != slices_per_line);
ret = intel_dp_dsc_compute_params(connector, pipe_config);
if (ret < 0) {
@ -2450,7 +2449,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
"Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
pipe_config->pipe_bpp,
FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
pipe_config->dsc.slice_count);
intel_dsc_line_slice_count(&pipe_config->dsc.slice_config));
return 0;
}

9
drivers/gpu/drm/i915/display/intel_vdsc.c
View File

@ -283,8 +283,9 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
pipe_config->dsc.slice_count);
vdsc_cfg->slice_width =
DIV_ROUND_UP(vdsc_cfg->pic_width,
intel_dsc_line_slice_count(&pipe_config->dsc.slice_config));
err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
@ -1042,7 +1043,7 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
drm_printf_indent(p, indent,
"dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n",
FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
crtc_state->dsc.slice_count,
intel_dsc_line_slice_count(&crtc_state->dsc.slice_config),
crtc_state->dsc.slice_config.streams_per_pipe);
}
@ -1078,7 +1079,7 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
struct intel_display *display = to_intel_display(crtc_state);
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
int htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
int dsc_slices = crtc_state->dsc.slice_count;
int dsc_slices = intel_dsc_line_slice_count(&crtc_state->dsc.slice_config);
int pixel_rate;
int min_cdclk;