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drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines

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Use REG_BIT & co. for PCH_TRANSCONF/TRANS_DP_CTL bits, and
adjust the naming a some bits to be more consistent.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211112193813.8224-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2021-11-12 21:38:09 +02:00
parent 6a6d914de3
commit e93a590c79
2 changed files with 33 additions and 38 deletions
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13
drivers/gpu/drm/i915/display/intel_pch_display.c
View File

@ -166,11 +166,11 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
if (HAS_PCH_IBX(dev_priv) &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
val |= TRANS_LEGACY_INTERLACED_ILK;
val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
else
val |= TRANS_INTERLACED;
val |= TRANS_INTERLACE_INTERLACED;
} else {
val |= TRANS_PROGRESSIVE;
val |= TRANS_INTERLACE_PROGRESSIVE;
}
intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
@ -293,7 +293,8 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp = intel_de_read(dev_priv, reg);
temp &= ~(TRANS_DP_PORT_SEL_MASK |
TRANS_DP_SYNC_MASK |
TRANS_DP_VSYNC_ACTIVE_HIGH |
TRANS_DP_HSYNC_ACTIVE_HIGH |
TRANS_DP_BPC_MASK);
temp |= TRANS_DP_OUTPUT_ENABLE;
temp |= bpc << 9; /* same format but at 11:9 */
@ -437,9 +438,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
val |= TRANS_INTERLACED;
val |= TRANS_INTERLACE_INTERLACED;
else
val |= TRANS_PROGRESSIVE;
val |= TRANS_INTERLACE_PROGRESSIVE;
intel_de_write(dev_priv, LPT_TRANSCONF, val);
if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,

58
drivers/gpu/drm/i915/i915_reg.h
View File

@ -8081,22 +8081,19 @@ enum {
#define _PCH_TRANSBCONF 0xf1008
#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
#define TRANS_DISABLE (0 << 31)
#define TRANS_ENABLE (1 << 31)
#define TRANS_STATE_MASK (1 << 30)
#define TRANS_STATE_DISABLE (0 << 30)
#define TRANS_STATE_ENABLE (1 << 30)
#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
#define TRANS_INTERLACE_MASK (7 << 21)
#define TRANS_PROGRESSIVE (0 << 21)
#define TRANS_INTERLACED (3 << 21)
#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
#define TRANS_8BPC (0 << 5)
#define TRANS_10BPC (1 << 5)
#define TRANS_6BPC (2 << 5)
#define TRANS_12BPC (3 << 5)
#define TRANS_ENABLE REG_BIT(31)
#define TRANS_STATE_ENABLE REG_BIT(30)
#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
#define _TRANSA_CHICKEN1 0xf0060
#define _TRANSB_CHICKEN1 0xf1060
#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
@ -8306,22 +8303,19 @@ enum {
#define _TRANS_DP_CTL_B 0xe1300
#define _TRANS_DP_CTL_C 0xe2300
#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
#define TRANS_DP_OUTPUT_ENABLE (1 << 31)
#define TRANS_DP_PORT_SEL_MASK (3 << 29)
#define TRANS_DP_PORT_SEL_NONE (3 << 29)
#define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
#define TRANS_DP_AUDIO_ONLY (1 << 26)
#define TRANS_DP_ENH_FRAMING (1 << 18)
#define TRANS_DP_8BPC (0 << 9)
#define TRANS_DP_10BPC (1 << 9)
#define TRANS_DP_6BPC (2 << 9)
#define TRANS_DP_12BPC (3 << 9)
#define TRANS_DP_BPC_MASK (3 << 9)
#define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
#define TRANS_DP_VSYNC_ACTIVE_LOW 0
#define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
#define TRANS_DP_HSYNC_ACTIVE_LOW 0
#define TRANS_DP_SYNC_MASK (3 << 3)
#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
#define TRANS_DP_ENH_FRAMING REG_BIT(18)
#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
#define _TRANS_DP2_CTL_A 0x600a0
#define _TRANS_DP2_CTL_B 0x610a0