diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index cb6abf80d1c9..b40e9865a33d 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -236,6 +236,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 #define LUCID_EVO_PLL_L_VAL_MASK	GENMASK(15, 0)
 #define LUCID_EVO_PLL_CAL_L_VAL_MASK	GENMASK(31, 16)
 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT	16
+#define LUCID_OLE_PROCESS_CAL_L_VAL_MASK	GENMASK(23, 16)
+#define LUCID_OLE_PROCESS_CAL_L_VAL_SHIFT	16
+#define LUCID_OLE_RINGOSC_CAL_L_VAL_MASK	GENMASK(31, 24)
+#define LUCID_OLE_RINGOSC_CAL_L_VAL_SHIFT	24
 
 /* ZONDA PLL specific */
 #define ZONDA_PLL_OUT_MASK	0xf
@@ -2977,14 +2981,22 @@ int clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll,
 		ret |= regmap_update_bits(regmap, PLL_L_VAL(pll),
 					LUCID_EVO_PLL_L_VAL_MASK, config->l);
 
-	if (config->cal_l)
+	if (config->cal_l_ringosc) {
 		ret |= regmap_update_bits(regmap, PLL_L_VAL(pll),
-				LUCID_EVO_PLL_CAL_L_VAL_MASK,
-				config->cal_l << LUCID_EVO_PLL_CAL_L_VAL_SHIFT);
-	else
+					  LUCID_OLE_PROCESS_CAL_L_VAL_MASK,
+					  config->cal_l << LUCID_OLE_PROCESS_CAL_L_VAL_SHIFT);
 		ret |= regmap_update_bits(regmap, PLL_L_VAL(pll),
-				LUCID_EVO_PLL_CAL_L_VAL_MASK,
-				TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT);
+					  LUCID_OLE_RINGOSC_CAL_L_VAL_MASK,
+					  config->cal_l_ringosc <<
+					  LUCID_OLE_RINGOSC_CAL_L_VAL_SHIFT);
+	} else if (config->cal_l) {
+		ret |= regmap_update_bits(regmap, PLL_L_VAL(pll),
+					  LUCID_EVO_PLL_CAL_L_VAL_MASK,
+					  config->cal_l << LUCID_EVO_PLL_CAL_L_VAL_SHIFT);
+	} else {
+		ret |= regmap_write(regmap, PLL_CAL_L_VAL(pll),
+				    TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT);
+	}
 
 	if (config->alpha)
 		ret |= regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 2a822fe211ba..785d9a6c4704 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -20,6 +20,7 @@ enum {
 	CLK_ALPHA_PLL_TYPE_ZONDA_5LPE,
 	CLK_ALPHA_PLL_TYPE_REGERA,
 	CLK_ALPHA_PLL_TYPE_LUCID_EVO,
+	CLK_ALPHA_PLL_TYPE_LUCID_OLE = CLK_ALPHA_PLL_TYPE_LUCID_EVO,
 	CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
 	CLK_ALPHA_PLL_TYPE_MAX,
 };
@@ -111,6 +112,7 @@ struct clk_alpha_pll_postdiv {
 struct alpha_pll_config {
 	u32 l;
 	u32 cal_l;
+	u32 cal_l_ringosc;
 	u32 alpha;
 	u32 alpha_hi;
 	u32 config_ctl_val;
@@ -170,6 +172,10 @@ extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
 
+#define clk_alpha_pll_lucid_ole_ops clk_alpha_pll_lucid_evo_ops
+#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
+#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
+
 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
 
 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@@ -193,6 +199,8 @@ int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 int clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll,
 				struct regmap *regmap,
 				const struct alpha_pll_config *config);
+#define clk_lucid_ole_pll_configure(pll, regmap, config) \
+	clk_lucid_evo_pll_configure(pll, regmap, config)
 int clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll,
 				struct regmap *regmap,
 				const struct alpha_pll_config *config);