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drm/rockchip: vop2: Do not divide height twice for YUV
For the cbcr format, gt2 and gt4 are computed again after src_h has been
divided by vsub.
As src_h as already been divided by 2 before, introduce cbcr_src_h and
cbcr_src_w to keep a copy of those values to be used for cbcr gt2 and
gt4 computation.
This fixes yuv planes being unaligned vertically when down scaling to
1080 pixels from 2160.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Fixes: 604be85547 ("drm/rockchip: Add VOP2 driver")
Acked-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20240414182706.655270-1-detlev.casanova@collabora.com
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parent
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@ -706,6 +706,8 @@ static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
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const struct drm_format_info *info;
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u16 hor_scl_mode, ver_scl_mode;
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u16 hscl_filter_mode, vscl_filter_mode;
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uint16_t cbcr_src_w = src_w;
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uint16_t cbcr_src_h = src_h;
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u8 gt2 = 0;
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u8 gt4 = 0;
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u32 val;
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@ -763,27 +765,27 @@ static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
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vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode);
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if (info->is_yuv) {
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src_w /= info->hsub;
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src_h /= info->vsub;
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cbcr_src_w /= info->hsub;
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cbcr_src_h /= info->vsub;
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gt4 = 0;
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gt2 = 0;
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if (src_h >= (4 * dst_h)) {
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if (cbcr_src_h >= (4 * dst_h)) {
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gt4 = 1;
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src_h >>= 2;
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} else if (src_h >= (2 * dst_h)) {
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cbcr_src_h >>= 2;
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} else if (cbcr_src_h >= (2 * dst_h)) {
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gt2 = 1;
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src_h >>= 1;
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cbcr_src_h >>= 1;
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}
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hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
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ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
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hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
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ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
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val = vop2_scale_factor(src_w, dst_w);
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val = vop2_scale_factor(cbcr_src_w, dst_w);
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vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val);
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val = vop2_scale_factor(src_h, dst_h);
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val = vop2_scale_factor(cbcr_src_h, dst_h);
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vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val);
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vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
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