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i2c: designware: size the RX FIFO threshold to the queued transfer
i2c_dw_xfer_msg() leaves DW_IC_RX_TL at the 0 that i2c_dw_configure_mode() writes, so the controller raises RX_FULL once per received byte. Program RX_TL from the reads already queued, capped at half the FIFO until the last message is queued, so there is room for the rest. On an Arrow Lake-H LPSS core with rx_fifo_depth 32, a 22-byte HID input report costs 2.00 interrupts instead of 21.43, and a 452-byte descriptor 0.14 interrupts per byte instead of 1.64. Polling the touchpad with HIDIOCGINPUT at 142 Hz draws 1.58 W less platform power (psys, 32 paired runs). Assisted-by: LLM Signed-off-by: Navon John Lukose <navonjohnlukose@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20261007191911.502428-1-navonjohnlukose@gmail.com
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@ -378,7 +378,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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u32 intr_mask;
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int tx_limit, rx_limit;
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int tx_limit, rx_limit, rx_tl;
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u32 buf_len = dev->tx_buf_len;
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u8 *buf = dev->tx_buf;
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bool need_restart = false;
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@ -484,6 +484,19 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
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if (dev->msg_err)
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intr_mask = 0;
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/*
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* Size the RX FIFO threshold to the reads already queued, so the
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* controller raises one RX_FULL for the whole burst instead of one per
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* received byte. While messages remain to be queued, cap it so RX_FULL
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* still arrives in time to drain the FIFO and let the next TX_EMPTY
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* queue the rest.
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*/
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rx_tl = dev->rx_outstanding;
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if (dev->msg_write_idx < dev->msgs_num)
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rx_tl = min_t(int, rx_tl, dev->rx_fifo_depth / 2);
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regmap_write(dev->map, DW_IC_RX_TL, rx_tl ? rx_tl - 1 : 0);
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__i2c_dw_write_intr_mask(dev, intr_mask);
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}
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