ASoC: cs530x: Correct MCLK reference frequency values

The MCLK frequency must be 49.152 MHz (for 48 kHz-related
sample rates) or 45.1584 MHz (for 44.1 kHz-related sample rates).

Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com>
Link: https://patch.msgid.link/20251023090327.58275-10-vitalyr@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vitaly Rodionov 2025-10-23 10:03:17 +01:00 committed by Mark Brown
parent c37c3e5e39
commit e7ab858390
2 changed files with 12 additions and 3 deletions

View File

@ -1100,9 +1100,12 @@ static int cs530x_set_sysclk(struct snd_soc_component *component, int clk_id,
switch (source) {
case CS530X_SYSCLK_SRC_MCLK:
if (freq != 24560000 && freq != 22572000) {
dev_err(component->dev, "Invalid MCLK source rate %d\n",
freq);
switch (freq) {
case CS530X_SYSCLK_REF_45_1MHZ:
case CS530X_SYSCLK_REF_49_1MHZ:
break;
default:
dev_err(component->dev, "Invalid MCLK source rate %d\n", freq);
return -EINVAL;
}
break;

View File

@ -200,6 +200,12 @@
/* IN_VOL_CTL5 and OUT_VOL_CTL5 */
#define CS530X_INOUT_VU BIT(0)
/* MCLK Reference Source Frequency */
/* 41KHz related */
#define CS530X_SYSCLK_REF_45_1MHZ 45158400
/* 48KHz related */
#define CS530X_SYSCLK_REF_49_1MHZ 49152000
/* System Clock Source */
#define CS530X_SYSCLK_SRC_MCLK 0
#define CS530X_SYSCLK_SRC_PLL 1