drm/rockchip: vop: add support csc and hdr

Change-Id: I64f1718646a9f94b4cb13035f1a852d6b824b5af
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang 2019-06-13 11:25:32 +08:00
parent 059bcbb1d0
commit e7aa22ba72
3 changed files with 951 additions and 85 deletions

View File

@ -33,12 +33,53 @@ struct drm_device;
struct drm_connector;
struct iommu_domain;
struct rockchip_atomic_commit {
struct drm_atomic_state *state;
struct drm_device *dev;
size_t bandwidth;
unsigned int plane_num;
};
struct rockchip_dclk_pll {
struct clk *pll;
unsigned int use_count;
};
struct rockchip_sdr2hdr_state {
int sdr2hdr_func;
bool bt1886eotf_pre_conv_en;
bool rgb2rgb_pre_conv_en;
bool rgb2rgb_pre_conv_mode;
bool st2084oetf_pre_conv_en;
bool bt1886eotf_post_conv_en;
bool rgb2rgb_post_conv_en;
bool rgb2rgb_post_conv_mode;
bool st2084oetf_post_conv_en;
};
struct rockchip_hdr_state {
bool pre_overlay;
bool hdr2sdr_en;
struct rockchip_sdr2hdr_state sdr2hdr_state;
};
struct rockchip_crtc_state {
struct drm_crtc_state base;
struct drm_tv_connector_state *tv_state;
int left_margin;
int right_margin;
int top_margin;
int bottom_margin;
int afbdc_win_format;
int afbdc_win_width;
int afbdc_win_height;
int afbdc_win_ptr;
int afbdc_win_id;
int afbdc_en;
int afbdc_win_vir_width;
int afbdc_win_xoffset;
int afbdc_win_yoffset;
int dsp_layer_sel;
int output_type;
int output_mode;
@ -51,6 +92,8 @@ struct rockchip_crtc_state {
int post_csc_mode;
int bcsh_en;
int color_space;
int eotf;
struct rockchip_hdr_state hdr;
struct drm_framebuffer *crtc_primary_fb;
};
#define to_rockchip_crtc_state(s) \
@ -83,6 +126,8 @@ struct rockchip_drm_private {
struct gen_pool *secure_buffer_pool;
struct mutex mm_lock;
struct drm_mm mm;
struct rockchip_dclk_pll default_pll;
struct rockchip_dclk_pll hdmi_pll;
struct list_head psr_list;
struct mutex psr_list_lock;
};

File diff suppressed because it is too large Load Diff

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@ -629,6 +629,14 @@ struct drm_color_lut {
__u16 reserved;
};
enum supported_eotf_type {
TRADITIONAL_GAMMA_SDR = 0,
TRADITIONAL_GAMMA_HDR,
SMPTE_ST2084,
HLG,
FUTURE_EOTF
};
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4