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clk: rockchip: Add new pll type pll_rk3588_ddr

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That PLL type is similar to the other rk3588 pll types but the actual
rate is twice the configured rate.
Therefore, the returned calculated rate must be multiplied by two.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Acked-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Elaine Zhang 2024-08-28 15:42:52 +00:00 committed by Heiko Stuebner
parent 49c04453db
commit e781bffc29
2 changed files with 6 additions and 1 deletions
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6
drivers/clk/rockchip/clk-pll.c
View File

@ -914,7 +914,10 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned
}
rate64 = rate64 >> cur.s;
return (unsigned long)rate64;
if (pll->type == pll_rk3588_ddr)
return (unsigned long)rate64 * 2;
else
return (unsigned long)rate64;
}
static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
break;
case pll_rk3588:
case pll_rk3588_core:
case pll_rk3588_ddr:
if (!pll->rate_table)
init.ops = &rockchip_rk3588_pll_clk_norate_ops;
else

1
drivers/clk/rockchip/clk.h
View File

@ -287,6 +287,7 @@ enum rockchip_pll_type {
pll_rk3399,
pll_rk3588,
pll_rk3588_core,
pll_rk3588_ddr,
};
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \