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RDMA/bnxt_re: Add support for QP rate limiting
Broadcom P7 chips supports applying rate limit to RC QPs. It allows adjust shaper rate values during the INIT -> RTR, RTR -> RTS, RTS -> RTS state changes or after QP transitions to RTR or RTS. Signed-off-by: Damodharam Ammepalli <damodharam.ammepalli@broadcom.com> Reviewed-by: Hongguang Gao <hongguang.gao@broadcom.com> Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Link: https://patch.msgid.link/20260202133413.3182578-2-kalesh-anakkur.purayil@broadcom.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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@ -2089,10 +2089,11 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
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unsigned int flags;
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u8 nw_type;
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if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
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if (qp_attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT))
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return -EOPNOTSUPP;
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qp->qplib_qp.modify_flags = 0;
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qp->qplib_qp.ext_modify_flags = 0;
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if (qp_attr_mask & IB_QP_STATE) {
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curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
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new_qp_state = qp_attr->qp_state;
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@ -2129,6 +2130,15 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
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bnxt_re_unlock_cqs(qp, flags);
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}
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}
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if (qp_attr_mask & IB_QP_RATE_LIMIT) {
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if (qp->qplib_qp.type != IB_QPT_RC ||
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!_is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2))
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return -EOPNOTSUPP;
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qp->qplib_qp.ext_modify_flags |=
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CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID;
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qp->qplib_qp.rate_limit = qp_attr->rate_limit;
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}
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if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
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qp->qplib_qp.modify_flags |=
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CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
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@ -1313,8 +1313,8 @@ int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)
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struct bnxt_qplib_cmdqmsg msg = {};
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struct cmdq_modify_qp req = {};
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u16 vlan_pcp_vlan_dei_vlan_id;
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u32 bmask, bmask_ext;
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u32 temp32[4];
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u32 bmask;
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int rc;
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bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
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@ -1329,9 +1329,16 @@ int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)
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is_optimized_state_transition(qp))
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bnxt_set_mandatory_attributes(res, qp, &req);
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}
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bmask = qp->modify_flags;
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req.modify_mask = cpu_to_le32(qp->modify_flags);
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bmask_ext = qp->ext_modify_flags;
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req.ext_modify_mask = cpu_to_le32(qp->ext_modify_flags);
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req.qp_cid = cpu_to_le32(qp->id);
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if (bmask_ext & CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID)
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req.rate_limit = cpu_to_le32(qp->rate_limit);
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if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_STATE) {
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req.network_type_en_sqd_async_notify_new_state =
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(qp->state & CMDQ_MODIFY_QP_NEW_STATE_MASK) |
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@ -1429,6 +1436,9 @@ int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)
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rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
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if (rc)
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return rc;
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if (bmask_ext & CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID)
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qp->shaper_allocation_status = resp.shaper_allocation_status;
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qp->cur_qp_state = qp->state;
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return 0;
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}
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@ -280,6 +280,7 @@ struct bnxt_qplib_qp {
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u8 state;
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u8 cur_qp_state;
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u64 modify_flags;
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u32 ext_modify_flags;
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u32 max_inline_data;
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u32 mtu;
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u8 path_mtu;
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@ -346,6 +347,8 @@ struct bnxt_qplib_qp {
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bool is_host_msn_tbl;
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u8 tos_dscp;
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u32 ugid_index;
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u32 rate_limit;
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u8 shaper_allocation_status;
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};
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#define BNXT_RE_MAX_MSG_SIZE 0x80000000
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@ -623,4 +623,10 @@ static inline bool _is_max_srq_ext_supported(u16 dev_cap_ext_flags_2)
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return !!(dev_cap_ext_flags_2 & CREQ_QUERY_FUNC_RESP_SB_MAX_SRQ_EXTENDED);
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}
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static inline bool _is_modify_qp_rate_limit_supported(u16 dev_cap_ext_flags2)
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{
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return dev_cap_ext_flags2 &
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CREQ_QUERY_FUNC_RESP_SB_MODIFY_QP_RATE_LIMIT_SUPPORTED;
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}
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#endif /* __BNXT_QPLIB_RES_H__ */
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@ -193,6 +193,11 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw)
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attr->max_dpi = le32_to_cpu(sb->max_dpi);
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attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw);
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if (_is_modify_qp_rate_limit_supported(attr->dev_cap_flags2)) {
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attr->rate_limit_min = le16_to_cpu(sb->rate_limit_min);
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attr->rate_limit_max = le32_to_cpu(sb->rate_limit_max);
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}
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bail:
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dma_free_coherent(&rcfw->pdev->dev, sbuf.size,
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sbuf.sb, sbuf.dma_addr);
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@ -76,6 +76,8 @@ struct bnxt_qplib_dev_attr {
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u16 dev_cap_flags;
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u16 dev_cap_flags2;
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u32 max_dpi;
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u16 rate_limit_min;
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u32 rate_limit_max;
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};
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struct bnxt_qplib_pd {
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@ -690,10 +690,11 @@ struct cmdq_modify_qp {
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__le32 ext_modify_mask;
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#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX 0x1UL
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#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID 0x2UL
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#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID 0x8UL
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__le32 ext_stats_ctx_id;
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__le16 schq_id;
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__le16 unused_0;
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__le32 reserved32;
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__le32 rate_limit;
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};
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/* creq_modify_qp_resp (size:128b/16B) */
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@ -716,7 +717,8 @@ struct creq_modify_qp_resp {
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#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL
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#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1
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#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL
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u8 reserved8;
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u8 shaper_allocation_status;
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#define CREQ_MODIFY_QP_RESP_SHAPER_ALLOCATED 0x1UL
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__le32 lag_src_mac;
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};
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@ -2179,7 +2181,7 @@ struct creq_query_func_resp {
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u8 reserved48[6];
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};
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/* creq_query_func_resp_sb (size:1088b/136B) */
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/* creq_query_func_resp_sb (size:1280b/160B) */
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struct creq_query_func_resp_sb {
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u8 opcode;
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#define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL
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@ -2256,12 +2258,15 @@ struct creq_query_func_resp_sb {
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#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST \
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CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE
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#define CREQ_QUERY_FUNC_RESP_SB_MAX_SRQ_EXTENDED 0x40UL
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#define CREQ_QUERY_FUNC_RESP_SB_MODIFY_QP_RATE_LIMIT_SUPPORTED 0x400UL
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#define CREQ_QUERY_FUNC_RESP_SB_MIN_RNR_RTR_RTS_OPT_SUPPORTED 0x1000UL
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__le16 max_xp_qp_size;
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__le16 create_qp_batch_size;
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__le16 destroy_qp_batch_size;
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__le16 max_srq_ext;
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__le64 reserved64;
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__le16 reserved16;
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__le16 rate_limit_min;
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__le32 rate_limit_max;
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};
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/* cmdq_set_func_resources (size:448b/56B) */
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