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arm64: dts: freescale: add initial device tree for TQMa91xx/MBa91xxCA
This adds support for TQMa91xx module attached to MBa91xxCA board. TQMa91xx is a SOM series using i.MX91 SOC. The SOM features PMIC, RAM, e-MMC and some optional peripherals like SPI-NOR, RTC, EEPROM, gyroscope and secure element. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Alexander Stein
Shawn Guo
parent
0f75caf42b
commit
e71db39f0c
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@ -340,6 +340,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
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imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo
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739
arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts
Normal file
739
arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts
Normal file
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@ -0,0 +1,739 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
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* D-82229 Seefeld, Germany.
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* Author: Markus Niebel
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* Author: Alexander Stein
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/usb/pd.h>
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#include "imx91-tqma9131.dtsi"
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/{
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model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa91xxCA starter kit";
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compatible = "tq,imx91-tqma9131-mba91xxca", "tq,imx91-tqma9131", "fsl,imx91";
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chassis-type = "embedded";
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chosen {
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stdout-path = &lpuart1;
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};
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aliases {
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eeprom0 = &eeprom0;
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ethernet0 = &eqos;
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ethernet1 = &fec;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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i2c0 = &lpi2c1;
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i2c1 = &lpi2c2;
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i2c2 = &lpi2c3;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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serial0 = &lpuart1;
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serial1 = &lpuart2;
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rtc0 = &pcf85063;
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rtc1 = &bbnsm_rtc;
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&tpm2 2 5000000 0>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <7>;
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power-supply = <®_12v0>;
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enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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display: display {
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/*
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* Display is not fixed, so compatible has to be added from
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* DT overlay
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*/
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power-supply = <®_3v3>;
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enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>;
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backlight = <&backlight>;
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status = "disabled";
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port {
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panel_in: endpoint {
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};
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};
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};
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fan0: gpio-fan {
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compatible = "gpio-fan";
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gpios = <&expander2 4 GPIO_ACTIVE_HIGH>;
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gpio-fan,speed-map = <0 0>, <10000 1>;
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fan-supply = <®_12v0>;
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#cooling-cells = <2>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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switch-a {
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label = "switcha";
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linux,code = <BTN_0>;
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gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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switch-b {
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label = "switchb";
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linux,code = <BTN_1>;
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gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led-1 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-on";
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};
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led-2 {
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_HEARTBEAT;
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gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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iio-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
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};
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lvds_encoder: lvds-encoder {
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compatible = "ti,sn75lvds83", "lvds-encoder";
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powerdown-gpios = <&expander2 3 GPIO_ACTIVE_LOW>;
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power-supply = <®_3v3>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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lvds_encoder_input: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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lvds_encoder_output: endpoint {
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};
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};
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};
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};
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reg_3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "V_3V3_MB";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_5v0: regulator-5v0 {
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compatible = "regulator-fixed";
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regulator-name = "V_5V0_MB";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_12v0: regulator-12v0 {
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compatible = "regulator-fixed";
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regulator-name = "V_12V";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_mpcie_1v5: regulator-mpcie-1v5 {
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compatible = "regulator-fixed";
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regulator-name = "V_1V5_MPCIE";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_mpcie_3v3: regulator-mpcie-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "V_3V3_MPCIE";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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};
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&adc1 {
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status = "okay";
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy_eqos>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy_eqos: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos_phy>;
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reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500000>;
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reset-deassert-us = <50000>;
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interrupt-parent = <&gpio3>;
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interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
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enet-phy-lane-no-swap;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy_fec>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <5000000>;
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ethphy_fec: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_phy>;
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reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500000>;
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reset-deassert-us = <50000>;
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interrupt-parent = <&gpio3>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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enet-phy-lane-no-swap;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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};
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};
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_3v3>;
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status = "okay";
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};
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&gpio1 {
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gpio-line-names =
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/* 00 */ "", "", "", "PMIC_IRQ#",
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/* 04 */ "", "", "", "",
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/* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#",
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/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",
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/* 16 */ "", "", "", "",
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/* 20 */ "", "", "", "",
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/* 24 */ "", "", "", "",
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/* 28 */ "", "", "", "";
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};
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&gpio2 {
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gpio-line-names =
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/* 00 */ "", "", "", "",
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/* 04 */ "", "", "", "",
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/* 08 */ "", "", "", "",
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/* 12 */ "", "", "", "",
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/* 16 */ "", "", "", "",
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/* 20 */ "", "", "", "",
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/* 24 */ "", "", "", "",
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/* 28 */ "", "", "", "";
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};
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&gpio3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_jtag>;
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gpio-line-names =
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/* 00 */ "SD2_CD#", "", "", "",
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/* 04 */ "", "", "", "SD2_RST#",
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/* 08 */ "", "", "", "",
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/* 12 */ "", "", "", "",
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/* 16 */ "", "", "", "",
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/* 20 */ "", "", "", "",
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/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",
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/* 28 */ "", "", "", "";
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};
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&gpio4 {
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gpio-line-names =
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/* 00 */ "", "", "", "",
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/* 04 */ "", "", "", "",
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/* 08 */ "", "", "", "",
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/* 12 */ "", "", "", "",
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/* 16 */ "", "", "", "",
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/* 20 */ "", "", "", "",
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/* 24 */ "", "", "", "",
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/* 28 */ "", "", "", "";
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};
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&lpi2c3 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpi2c3>;
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pinctrl-1 = <&pinctrl_lpi2c3>;
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status = "okay";
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temperature-sensor@1c {
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compatible = "nxp,se97b", "jedec,jc-42.4-temp";
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reg = <0x1c>;
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};
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ptn5110: usb-typec@50 {
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compatible = "nxp,ptn5110", "tcpci";
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reg = <0x50>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_typec>;
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interrupt-parent = <&gpio1>;
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interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
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connector {
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compatible = "usb-c-connector";
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label = "X17";
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power-role = "dual";
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data-role = "dual";
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try-power-role = "sink";
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typec-power-opmode = "default";
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pd-disable;
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self-powered;
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port {
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typec_con_hs: endpoint {
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remote-endpoint = <&typec_hs>;
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};
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};
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};
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};
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eeprom2: eeprom@54 {
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compatible = "nxp,se97b", "atmel,24c02";
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reg = <0x54>;
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pagesize = <16>;
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vcc-supply = <®_3v3>;
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};
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expander0: gpio@70 {
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compatible = "nxp,pca9538";
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reg = <0x70>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pexp_irq>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gpio1>;
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interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
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vcc-supply = <®_3v3>;
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gpio-line-names = "TEMP_EVENT_MOD#", "MPCIE_WAKE#",
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"MPCIE_1V5_EN", "MPCIE_3V3_EN",
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"MPCIE_PERST#", "MPCIE_WDISABLE#",
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"BUTTON_A#", "BUTTON_B#";
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temp-event-mod-hog {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_LOW>;
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input;
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line-name = "TEMP_EVENT_MOD#";
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};
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mpcie-wake-hog {
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_LOW>;
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input;
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line-name = "MPCIE_WAKE#";
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};
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/*
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* Controls the mPCIE slot reset which is low active as
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* reset signal. The output-low states, the signal is
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* inactive, e.g. not in reset
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*/
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mpcie_rst_hog: mpcie-rst-hog {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "MPCIE_PERST#";
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};
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/*
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* Controls the mPCIE slot WDISABLE pin which is low active
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* as disable signal. The output-low states, the signal is
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* inactive, e.g. not disabled
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*/
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mpcie_wdisable_hog: mpcie-wdisable-hog {
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gpio-hog;
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gpios = <5 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "MPCIE_WDISABLE#";
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};
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};
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expander1: gpio@71 {
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compatible = "nxp,pca9538";
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reg = <0x71>;
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gpio-controller;
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#gpio-cells = <2>;
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vcc-supply = <®_3v3>;
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gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
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"USB_RESET#", "",
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"WLAN_PD#", "WLAN_W_DISABLE#",
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"WLAN_PERST#", "12V_EN";
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/*
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* Controls the WiFi card PD pin which is low active
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* as power down signal. The output-low states, the signal
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* is inactive, e.g. not power down
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*/
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wlan-pd-hog {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "WLAN_PD#";
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};
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/*
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* Controls the WiFi card disable pin which is low active
|
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* as disable signal. The output-low states, the signal
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* is inactive, e.g. not disabled
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*/
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wlan-wdisable-hog {
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gpio-hog;
|
||||
gpios = <5 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "WLAN_W_DISABLE#";
|
||||
};
|
||||
|
||||
/*
|
||||
* Controls the WiFi card reset pin which is low active
|
||||
* as reset signal. The output-low states, the signal
|
||||
* is inactive, e.g. not in reset
|
||||
*/
|
||||
wlan-perst-hog {
|
||||
gpio-hog;
|
||||
gpios = <6 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "WLAN_PERST#";
|
||||
};
|
||||
};
|
||||
|
||||
expander2: gpio@72 {
|
||||
compatible = "nxp,pca9538";
|
||||
reg = <0x72>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <®_3v3>;
|
||||
gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
|
||||
"LCD_BLT_EN", "LVDS_SHDN#",
|
||||
"FAN_PWR_EN", "",
|
||||
"USER_LED1", "USER_LED2";
|
||||
};
|
||||
};
|
||||
|
||||
&lpuart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpuart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcf85063 {
|
||||
/* RTC_EVENT# from SoM is connected on mainboard */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcf85063>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
&se97_som {
|
||||
/* TEMP_EVENT# from SoM is connected on mainboard */
|
||||
interrupt-parent = <&expander0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
&tpm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tpm2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
dr_mode = "otg";
|
||||
hnp-disable;
|
||||
srp-disable;
|
||||
adp-disable;
|
||||
usb-role-switch;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
typec_hs: endpoint {
|
||||
remote-endpoint = <&typec_con_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
|
||||
hub_2_0: hub@1 {
|
||||
compatible = "usb424,2517";
|
||||
reg = <1>;
|
||||
reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
|
||||
vdd-supply = <®_3v3>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
disable-wp;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_eqos: eqosgrp {
|
||||
fsl,pins = /* PD | FSEL_2 | DSE X4 */
|
||||
<MX91_PAD_ENET1_MDC__ENET1_MDC 0x51e>,
|
||||
/* SION | HYS | FSEL_2 | DSE X4 */
|
||||
<MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e>,
|
||||
/* HYS | FSEL_0 | DSE no drive */
|
||||
<MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000>,
|
||||
<MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000>,
|
||||
<MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000>,
|
||||
<MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000>,
|
||||
<MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000>,
|
||||
/* HYS | PD | FSEL_0 | DSE no drive */
|
||||
<MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x1400>,
|
||||
/* PD | FSEL_2 | DSE X4 */
|
||||
<MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e>,
|
||||
<MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x51e>,
|
||||
<MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e>,
|
||||
<MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e>,
|
||||
<MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e>,
|
||||
/* PD | FSEL_3 | DSE X3 */
|
||||
<MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e>;
|
||||
};
|
||||
|
||||
pinctrl_eqos_phy: eqosphygrp {
|
||||
fsl,pins = /* HYS | FSEL_0 | DSE no drive */
|
||||
<MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = /* PD | FSEL_2 | DSE X4 */
|
||||
<MX91_PAD_ENET2_MDC__ENET2_MDC 0x51e>,
|
||||
/* SION | HYS | FSEL_2 | DSE X4 */
|
||||
<MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x4000111e>,
|
||||
/* HYS | FSEL_0 | DSE no drive */
|
||||
<MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x1000>,
|
||||
<MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x1000>,
|
||||
<MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x1000>,
|
||||
<MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x1000>,
|
||||
<MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x1000>,
|
||||
/* HYS | PD | FSEL_0 | DSE no drive */
|
||||
<MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x1400>,
|
||||
/* PD | FSEL_2 | DSE X4 */
|
||||
<MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x51e>,
|
||||
<MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x51e>,
|
||||
<MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x51e>,
|
||||
<MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x51e>,
|
||||
<MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x51e>,
|
||||
/* PD | FSEL_3 | DSE X3 */
|
||||
<MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x58e>;
|
||||
};
|
||||
|
||||
pinctrl_fec_phy: fecphygrp {
|
||||
fsl,pins = /* HYS | FSEL_0 | DSE no drive */
|
||||
<MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */
|
||||
<MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200>,
|
||||
/* PU | FSEL_3 | DSE X4 */
|
||||
<MX91_PAD_PDM_CLK__CAN1_TX 0x039e>;
|
||||
};
|
||||
|
||||
pinctrl_jtag: jtaggrp {
|
||||
fsl,pins = <MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e>,
|
||||
<MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200>,
|
||||
<MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e>,
|
||||
<MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200>;
|
||||
};
|
||||
|
||||
pinctrl_lpi2c3: lpi2c3grp {
|
||||
fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */
|
||||
<MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e>,
|
||||
<MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e>;
|
||||
};
|
||||
|
||||
pinctrl_pcf85063: pcf85063grp {
|
||||
fsl,pins = <MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl_pexp_irq: pexpirqgrp {
|
||||
fsl,pins = /* HYS | FSEL_0 | No DSE */
|
||||
<MX91_PAD_SAI1_TXC__GPIO1_IO12 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl_rgbdisp: rgbdispgrp {
|
||||
fsl,pins = <MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e>,
|
||||
<MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e>,
|
||||
<MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e>,
|
||||
<MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e>,
|
||||
<MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e>,
|
||||
<MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e>,
|
||||
<MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e>,
|
||||
<MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e>,
|
||||
<MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e>,
|
||||
<MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e>,
|
||||
<MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e>,
|
||||
<MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e>,
|
||||
<MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e>,
|
||||
<MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e>,
|
||||
<MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e>,
|
||||
<MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e>,
|
||||
<MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e>,
|
||||
<MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e>,
|
||||
<MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e>,
|
||||
<MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e>,
|
||||
<MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e>,
|
||||
<MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e>,
|
||||
<MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x31e>,
|
||||
<MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x31e>,
|
||||
<MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x31e>,
|
||||
<MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x31e>,
|
||||
<MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x31e>,
|
||||
<MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x31e>;
|
||||
};
|
||||
|
||||
pinctrl_touch: touchgrp {
|
||||
fsl,pins = /* HYS | FSEL_0 | No DSE */
|
||||
<MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl_tpm2: tpm2grp {
|
||||
fsl,pins = <MX91_PAD_I2C2_SCL__TPM2_CH2 0x57e>;
|
||||
};
|
||||
|
||||
pinctrl_typec: typecgrp {
|
||||
fsl,pins = /* HYS | FSEL_0 | No DSE */
|
||||
<MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = /* HYS | FSEL_0 | No DSE */
|
||||
<MX91_PAD_UART1_RXD__LPUART1_RX 0x1000>,
|
||||
/* FSEL_2 | DSE X4 */
|
||||
<MX91_PAD_UART1_TXD__LPUART1_TX 0x011e>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = /* HYS | FSEL_0 | No DSE */
|
||||
<MX91_PAD_UART2_RXD__LPUART2_RX 0x1000>,
|
||||
/* FSEL_2 | DSE X4 */
|
||||
<MX91_PAD_UART2_TXD__LPUART2_TX 0x011e>,
|
||||
/* FSEL_2 | DSE X4 */
|
||||
<MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||||
fsl,pins = /* HYS | FSEL_0 | No DSE */
|
||||
<MX91_PAD_SD2_CD_B__GPIO3_IO0 0x1000>;
|
||||
};
|
||||
|
||||
/* enable SION for data and cmd pad due to ERR052021 */
|
||||
pinctrl_usdhc2_hs: usdhc2hsgrp {
|
||||
fsl,pins = /* PD | FSEL_3 | DSE X5 */
|
||||
<MX91_PAD_SD2_CLK__USDHC2_CLK 0x05be>,
|
||||
/* HYS | PU | FSEL_3 | DSE X4 */
|
||||
<MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>,
|
||||
/* HYS | PU | FSEL_3 | DSE X3 */
|
||||
<MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e>,
|
||||
<MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e>,
|
||||
<MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e>,
|
||||
<MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e>,
|
||||
/* FSEL_2 | DSE X3 */
|
||||
<MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>;
|
||||
};
|
||||
|
||||
/* enable SION for data and cmd pad due to ERR052021 */
|
||||
pinctrl_usdhc2_uhs: usdhc2uhsgrp {
|
||||
fsl,pins = /* PD | FSEL_3 | DSE X6 */
|
||||
<MX91_PAD_SD2_CLK__USDHC2_CLK 0x05fe>,
|
||||
/* HYS | PU | FSEL_3 | DSE X4 */
|
||||
<MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>,
|
||||
<MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e>,
|
||||
<MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e>,
|
||||
<MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e>,
|
||||
<MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e>,
|
||||
/* FSEL_2 | DSE X3 */
|
||||
<MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>;
|
||||
};
|
||||
};
|
||||
295
arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi
Normal file
295
arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi
Normal file
|
|
@ -0,0 +1,295 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
|
||||
* D-82229 Seefeld, Germany.
|
||||
* Author: Markus Niebel
|
||||
* Author: Alexander Stein
|
||||
*/
|
||||
|
||||
#include "imx91.dtsi"
|
||||
|
||||
/{
|
||||
model = "TQ-Systems i.MX91 TQMa91xxCA / TQMa91xxLA SOM";
|
||||
compatible = "tq,imx91-tqma9131", "fsl,imx91";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* our minimum RAM config will be 1024 MiB */
|
||||
reg = <0x00000000 0x80000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* default CMA, must not exceed assembled memory */
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
alloc-ranges = <0 0x80000000 0 0x40000000>;
|
||||
size = <0 0x10000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
|
||||
/* EdgeLock secure enclave */
|
||||
ele_reserved: ele-reserved@a4120000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa4120000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
/* SD2 RST# via PMIC SW_EN */
|
||||
reg_usdhc2_vmmc: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&buck4>;
|
||||
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&adc1 {
|
||||
vref-supply = <&buck5>;
|
||||
};
|
||||
|
||||
&flexspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexspi1>;
|
||||
status = "okay";
|
||||
|
||||
flash0: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
/*
|
||||
* no DQS, RXCLKSRC internal loop back, max 66 MHz
|
||||
* clk framework uses CLK_DIVIDER_ROUND_CLOSEST
|
||||
* selected value together with root from
|
||||
* IMX91_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to
|
||||
* respect the maximum value.
|
||||
*/
|
||||
spi-max-frequency = <62000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
vcc-supply = <&buck5>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lpi2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pinctrl_lpi2c1>;
|
||||
pinctrl-1 = <&pinctrl_lpi2c1>;
|
||||
status = "okay";
|
||||
|
||||
se97_som: temperature-sensor@1b {
|
||||
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
|
||||
reg = <0x1b>;
|
||||
};
|
||||
|
||||
pca9451a: pmic@25 {
|
||||
compatible = "nxp,pca9451a";
|
||||
reg = <0x25>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pca9451>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulators {
|
||||
/* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */
|
||||
buck1: BUCK1 {
|
||||
regulator-name = "BUCK1";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
/* V_DDRQ - 1.1 V for LPDDR4 */
|
||||
buck2: BUCK2 {
|
||||
regulator-name = "BUCK2";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
/* V_3V3 - EEPROM, RTC, ... */
|
||||
buck4: BUCK4 {
|
||||
regulator-name = "BUCK4";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_1V8 - SPI NOR, eMMC, RAM VDD1... */
|
||||
buck5: BUCK5 {
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_1V1 - RAM VDD2*/
|
||||
buck6: BUCK6 {
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_1V8_BBSM, fix 1.8 */
|
||||
ldo1: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_0V8_ANA */
|
||||
ldo4: LDO4 {
|
||||
regulator-name = "LDO4";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_SD2 - 3.3/1.8V USDHC2 io Voltage */
|
||||
ldo5: LDO5 {
|
||||
regulator-name = "LDO5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcf85063: rtc@51 {
|
||||
compatible = "nxp,pcf85063a";
|
||||
reg = <0x51>;
|
||||
quartz-load-femtofarads = <7000>;
|
||||
};
|
||||
|
||||
eeprom0: eeprom@53 {
|
||||
compatible = "nxp,se97b", "atmel,24c02";
|
||||
reg = <0x53>;
|
||||
pagesize = <16>;
|
||||
read-only;
|
||||
vcc-supply = <&buck4>;
|
||||
};
|
||||
|
||||
eeprom1: eeprom@57 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x57>;
|
||||
pagesize = <32>;
|
||||
vcc-supply = <&buck4>;
|
||||
};
|
||||
|
||||
/* protectable identification memory (part of M24C64-D @57) */
|
||||
eeprom@5f {
|
||||
compatible = "atmel,24c64d-wl";
|
||||
reg = <0x5f>;
|
||||
vcc-supply = <&buck4>;
|
||||
};
|
||||
|
||||
accelerometer@6a {
|
||||
compatible = "st,ism330dhcx";
|
||||
reg = <0x6a>;
|
||||
vdd-supply = <&buck4>;
|
||||
vddio-supply = <&buck4>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1>;
|
||||
vmmc-supply = <&buck4>;
|
||||
vqmmc-supply = <&buck5>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_flexspi1: flexspi1grp {
|
||||
fsl,pins = /* FSEL 3 | DSE X6 */
|
||||
<MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x01fe>,
|
||||
<MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x01fe>,
|
||||
/* HYS | PU | FSEL 3 | DSE X6 */
|
||||
<MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x13fe>,
|
||||
<MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x13fe>,
|
||||
/* HYS | FSEL 3 | DSE X6 (external PU) */
|
||||
<MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x11fe>,
|
||||
<MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x11fe>;
|
||||
};
|
||||
|
||||
pinctrl_lpi2c1: lpi2c1grp {
|
||||
fsl,pins = /* SION | OD | FSEL 3 | DSE X4 */
|
||||
<MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x4000199e>,
|
||||
<MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x4000199e>;
|
||||
};
|
||||
|
||||
pinctrl_pca9451: pca9451grp {
|
||||
fsl,pins = /* HYS | PU */
|
||||
<MX91_PAD_I2C2_SDA__GPIO1_IO3 0x1200>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||||
fsl,pins = /* FSEL 2 | DSE X2 */
|
||||
<MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x106>;
|
||||
};
|
||||
|
||||
/* enable SION for data and cmd pad due to ERR052021 */
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = /* PD | FSEL 3 | DSE X5 */
|
||||
<MX91_PAD_SD1_CLK__USDHC1_CLK 0x5be>,
|
||||
/* HYS | FSEL 0 | no drive */
|
||||
<MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1000>,
|
||||
/* HYS | FSEL 3 | X5 */
|
||||
<MX91_PAD_SD1_CMD__USDHC1_CMD 0x400011be>,
|
||||
/* HYS | FSEL 3 | X4 */
|
||||
<MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e>,
|
||||
<MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e>,
|
||||
<MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e>,
|
||||
<MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e>,
|
||||
<MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e>,
|
||||
<MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e>,
|
||||
<MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e>,
|
||||
<MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = /* PU | FSEL 1 | DSE X4 */
|
||||
<MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user