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drm/xe: Promote struct xe_tile definition to own file
We already have separate .c and .h files for xe_tile functions, time to introduce _types.h to follow what other components do. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260203211240.745-4-michal.wajdeczko@intel.com
This commit is contained in:
Michal Wajdeczko
parent
ed61c18617
commit
e7002e0eb4
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@ -15,10 +15,6 @@
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#include "xe_devcoredump_types.h"
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#include "xe_heci_gsc.h"
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#include "xe_late_bind_fw_types.h"
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#include "xe_lmtt_types.h"
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#include "xe_memirq_types.h"
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#include "xe_mert.h"
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#include "xe_mmio_types.h"
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#include "xe_oa_types.h"
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#include "xe_pagefault_types.h"
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#include "xe_platform_types.h"
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@ -30,7 +26,7 @@
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#include "xe_sriov_vf_ccs_types.h"
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#include "xe_step_types.h"
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#include "xe_survivability_mode_types.h"
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#include "xe_tile_sriov_vf_types.h"
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#include "xe_tile_types.h"
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#include "xe_validation.h"
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#if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
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@ -96,129 +92,6 @@ enum xe_wedged_mode {
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(_xe)->info.step.graphics >= (min_step) && \
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(_xe)->info.step.graphics < (max_step))
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#define tile_to_xe(tile__) \
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_Generic(tile__, \
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const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \
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struct xe_tile * : (tile__)->xe)
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/**
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* struct xe_tile - hardware tile structure
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*
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* From a driver perspective, a "tile" is effectively a complete GPU, containing
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* an SGunit, 1-2 GTs, and (for discrete platforms) VRAM.
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*
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* Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
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* device and designate one "root" tile as being responsible for external PCI
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* communication. PCI BAR0 exposes the GGTT and MMIO register space for each
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* tile in a stacked layout, and PCI BAR2 exposes the local memory associated
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* with each tile similarly. Device-wide interrupts can be enabled/disabled
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* at the root tile, and the MSTR_TILE_INTR register will report which tiles
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* have interrupts that need servicing.
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*/
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struct xe_tile {
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/** @xe: Backpointer to tile's PCI device */
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struct xe_device *xe;
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/** @id: ID of the tile */
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u8 id;
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/**
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* @primary_gt: Primary GT
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*/
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struct xe_gt *primary_gt;
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/**
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* @media_gt: Media GT
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*
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* Only present on devices with media version >= 13.
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*/
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struct xe_gt *media_gt;
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/**
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* @mmio: MMIO info for a tile.
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*
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* Each tile has its own 16MB space in BAR0, laid out as:
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* * 0-4MB: registers
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* * 4MB-8MB: reserved
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* * 8MB-16MB: global GTT
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*/
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struct xe_mmio mmio;
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/** @mem: memory management info for tile */
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struct {
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/**
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* @mem.kernel_vram: kernel-dedicated VRAM info for tile.
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*
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* Although VRAM is associated with a specific tile, it can
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* still be accessed by all tiles' GTs.
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*/
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struct xe_vram_region *kernel_vram;
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/**
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* @mem.vram: general purpose VRAM info for tile.
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*
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* Although VRAM is associated with a specific tile, it can
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* still be accessed by all tiles' GTs.
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*/
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struct xe_vram_region *vram;
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/** @mem.ggtt: Global graphics translation table */
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struct xe_ggtt *ggtt;
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/**
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* @mem.kernel_bb_pool: Pool from which batchbuffers are allocated.
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*
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* Media GT shares a pool with its primary GT.
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*/
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struct xe_sa_manager *kernel_bb_pool;
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/**
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* @mem.reclaim_pool: Pool for PRLs allocated.
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*
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* Only main GT has page reclaim list allocations.
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*/
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struct xe_sa_manager *reclaim_pool;
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} mem;
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/** @sriov: tile level virtualization data */
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union {
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struct {
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/** @sriov.pf.lmtt: Local Memory Translation Table. */
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struct xe_lmtt lmtt;
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} pf;
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struct {
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/** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
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struct xe_ggtt_node *ggtt_balloon[2];
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/** @sriov.vf.self_config: VF configuration data */
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struct xe_tile_sriov_vf_selfconfig self_config;
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} vf;
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} sriov;
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/** @memirq: Memory Based Interrupts. */
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struct xe_memirq memirq;
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/** @csc_hw_error_work: worker to report CSC HW errors */
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struct work_struct csc_hw_error_work;
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/** @pcode: tile's PCODE */
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struct {
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/** @pcode.lock: protecting tile's PCODE mailbox data */
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struct mutex lock;
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} pcode;
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/** @migrate: Migration helper for vram blits and clearing */
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struct xe_migrate *migrate;
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/** @sysfs: sysfs' kobj used by xe_tile_sysfs */
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struct kobject *sysfs;
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/** @debugfs: debugfs directory associated with this tile */
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struct dentry *debugfs;
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/** @mert: MERT-related data */
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struct xe_mert mert;
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};
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/**
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* struct xe_device - Top level struct of Xe device
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*/
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141
drivers/gpu/drm/xe/xe_tile_types.h
Normal file
141
drivers/gpu/drm/xe/xe_tile_types.h
Normal file
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@ -0,0 +1,141 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022-2026 Intel Corporation
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*/
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#ifndef _XE_TILE_TYPES_H_
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#define _XE_TILE_TYPES_H_
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#include <linux/mutex_types.h>
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#include <linux/workqueue_types.h>
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#include "xe_lmtt_types.h"
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#include "xe_memirq_types.h"
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#include "xe_mert.h"
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#include "xe_mmio_types.h"
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#include "xe_tile_sriov_vf_types.h"
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#define tile_to_xe(tile__) \
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_Generic(tile__, \
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const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \
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struct xe_tile * : (tile__)->xe)
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/**
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* struct xe_tile - hardware tile structure
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*
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* From a driver perspective, a "tile" is effectively a complete GPU, containing
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* an SGunit, 1-2 GTs, and (for discrete platforms) VRAM.
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*
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* Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
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* device and designate one "root" tile as being responsible for external PCI
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* communication. PCI BAR0 exposes the GGTT and MMIO register space for each
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* tile in a stacked layout, and PCI BAR2 exposes the local memory associated
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* with each tile similarly. Device-wide interrupts can be enabled/disabled
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* at the root tile, and the MSTR_TILE_INTR register will report which tiles
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* have interrupts that need servicing.
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*/
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struct xe_tile {
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/** @xe: Backpointer to tile's PCI device */
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struct xe_device *xe;
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/** @id: ID of the tile */
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u8 id;
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/**
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* @primary_gt: Primary GT
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*/
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struct xe_gt *primary_gt;
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/**
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* @media_gt: Media GT
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*
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* Only present on devices with media version >= 13.
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*/
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struct xe_gt *media_gt;
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/**
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* @mmio: MMIO info for a tile.
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*
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* Each tile has its own 16MB space in BAR0, laid out as:
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* * 0-4MB: registers
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* * 4MB-8MB: reserved
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* * 8MB-16MB: global GTT
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*/
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struct xe_mmio mmio;
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/** @mem: memory management info for tile */
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struct {
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/**
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* @mem.kernel_vram: kernel-dedicated VRAM info for tile.
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*
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* Although VRAM is associated with a specific tile, it can
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* still be accessed by all tiles' GTs.
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*/
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struct xe_vram_region *kernel_vram;
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/**
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* @mem.vram: general purpose VRAM info for tile.
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*
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* Although VRAM is associated with a specific tile, it can
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* still be accessed by all tiles' GTs.
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*/
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struct xe_vram_region *vram;
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/** @mem.ggtt: Global graphics translation table */
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struct xe_ggtt *ggtt;
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/**
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* @mem.kernel_bb_pool: Pool from which batchbuffers are allocated.
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*
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* Media GT shares a pool with its primary GT.
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*/
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struct xe_sa_manager *kernel_bb_pool;
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/**
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* @mem.reclaim_pool: Pool for PRLs allocated.
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*
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* Only main GT has page reclaim list allocations.
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*/
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struct xe_sa_manager *reclaim_pool;
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} mem;
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/** @sriov: tile level virtualization data */
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union {
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struct {
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/** @sriov.pf.lmtt: Local Memory Translation Table. */
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struct xe_lmtt lmtt;
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} pf;
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struct {
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/** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
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struct xe_ggtt_node *ggtt_balloon[2];
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/** @sriov.vf.self_config: VF configuration data */
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struct xe_tile_sriov_vf_selfconfig self_config;
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} vf;
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} sriov;
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/** @memirq: Memory Based Interrupts. */
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struct xe_memirq memirq;
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/** @csc_hw_error_work: worker to report CSC HW errors */
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struct work_struct csc_hw_error_work;
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/** @pcode: tile's PCODE */
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struct {
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/** @pcode.lock: protecting tile's PCODE mailbox data */
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struct mutex lock;
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} pcode;
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/** @migrate: Migration helper for vram blits and clearing */
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struct xe_migrate *migrate;
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/** @sysfs: sysfs' kobj used by xe_tile_sysfs */
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struct kobject *sysfs;
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/** @debugfs: debugfs directory associated with this tile */
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struct dentry *debugfs;
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/** @mert: MERT-related data */
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struct xe_mert mert;
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};
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#endif
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