From e6b8e7f217c772b53491ecf395748ba409ba181b Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Fri, 7 Aug 2026 19:24:31 -0600 Subject: [PATCH] RISC-V: Define indirect CSR access helpers The indirect CSR requires multiple instructions to read/write CSR. Add a few helper macros for ease of usage. These have to be macros rather than functions. csr_read()/csr_write() stringify their CSR argument into the inline asm template via __ASM_STR(), so the CSR number must be a literal token; passing it as a function parameter emits "csrr %0, iregcsr", which the assembler rejects with "unknown CSR `iregcsr'". The stringification happens in the preprocessor, before inlining or constant propagation, so it cannot be worked around by forcing inlining or by only ever passing constants - gcc 12, gcc 16 and clang 22 all reject it alike. Underneath, csrr/csrw encode the CSR as a 12-bit immediate and RISC-V has no register-indirect form, which is also why asm/csr.h keeps every one of its accessors as a macro. Signed-off-by: Atish Patra Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins [pjw@kernel.org: expand "ind" abbreviation] Link: https://patch.msgid.link/20260807-counter_delegation-v9-5-58658104e487@meta.com Signed-off-by: Paul Walmsley --- arch/riscv/include/asm/csr_indirect.h | 50 +++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 arch/riscv/include/asm/csr_indirect.h diff --git a/arch/riscv/include/asm/csr_indirect.h b/arch/riscv/include/asm/csr_indirect.h new file mode 100644 index 000000000000..0f558fac8f5f --- /dev/null +++ b/arch/riscv/include/asm/csr_indirect.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ASM_RISCV_CSR_INDIRECT_H +#define _ASM_RISCV_CSR_INDIRECT_H + +#include + +#include + +/* + * These have to be macros rather than functions: csr_read()/csr_write() + * stringify their CSR argument into the inline asm template via __ASM_STR(), + * so the CSR number must be a literal token at preprocessing time. Passing it + * as a function parameter emits "csrr %0, iregcsr", which no assembler can + * resolve. RISC-V has no register-indirect form of csrr/csrw - the CSR is a + * 12-bit immediate - so the sireg CSR selecting the indirect window cannot + * itself be a variable. + */ +#define csr_indirect_read(iregcsr, iselbase, iseloff) ({ \ + unsigned long __value = 0; \ + unsigned long __flags; \ + local_irq_save(__flags); \ + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \ + __value = csr_read(iregcsr); \ + local_irq_restore(__flags); \ + __value; \ +}) + +#define csr_indirect_write(iregcsr, iselbase, iseloff, value) ({ \ + unsigned long __flags; \ + local_irq_save(__flags); \ + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \ + csr_write(iregcsr, (value)); \ + local_irq_restore(__flags); \ +}) + +#define csr_indirect_warl(iregcsr, iselbase, iseloff, warl_val) ({ \ + unsigned long __old_val = 0, __value = 0; \ + unsigned long __flags; \ + local_irq_save(__flags); \ + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \ + __old_val = csr_read(iregcsr); \ + csr_write(iregcsr, (warl_val)); \ + __value = csr_read(iregcsr); \ + csr_write(iregcsr, __old_val); \ + local_irq_restore(__flags); \ + __value; \ +}) + +#endif