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drm/tidss: dispc: Switch REG_FLD_MOD to using a mask

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The REG_FLD_MOD function takes the start and end bits as parameter and
will generate a mask out of them.

This makes it difficult to share the masks between callers, since we now
need two arguments and to keep them consistent.

Let's change REG_FLD_MOD to take the mask as an argument instead, and
let the caller create the mask. Eventually, this mask will be moved to a
define.

Signed-off-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20250827-drm-tidss-field-api-v3-8-7689b664cc63@kernel.org
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
This commit is contained in:
Maxime Ripard 2025-08-27 17:12:39 +02:00 committed by Tomi Valkeinen
parent 8bd839a3ec
commit e6b571e6ff
1 changed files with 9 additions and 9 deletions
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18
drivers/gpu/drm/tidss/tidss_dispc.c
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@ -597,12 +597,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport)
#define REG_GET(dispc, idx, mask) \
((u32)FIELD_GET((mask), dispc_read((dispc), (idx))))
#define REG_FLD_MOD(dispc, idx, val, start, end) \
#define REG_FLD_MOD(dispc, idx, val, mask) \
({ \
struct dispc_device *_dispc = (dispc); \
u32 _idx = (idx); \
u32 _reg = dispc_read(_dispc, _idx); \
FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \
FIELD_MODIFY((mask), &_reg, (val)); \
dispc_write(_dispc, _idx, _reg); \
})
@ -2318,9 +2318,9 @@ static void dispc_k2g_plane_init(struct dispc_device *dispc)
dev_dbg(dispc->dev, "%s()\n", __func__);
/* MFLAG_CTRL = ENABLED */
REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0));
/* MFLAG_START = MFLAGNORMALSTARTMODE */
REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6));
for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) {
u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
@ -2369,13 +2369,13 @@ static void dispc_k3_plane_init(struct dispc_device *dispc)
dev_dbg(dispc->dev, "%s()\n", __func__);
REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0);
REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3);
REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, GENMASK(2, 0));
REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, GENMASK(5, 3));
/* MFLAG_CTRL = ENABLED */
REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0));
/* MFLAG_START = MFLAGNORMALSTARTMODE */
REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6));
for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) {
u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
@ -2903,7 +2903,7 @@ static int dispc_softreset(struct dispc_device *dispc)
}
/* Soft reset */
REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, GENMASK(1, 1));
/* Wait for reset to complete */
ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS,
val, val & 1, 100, 5000);