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- Fix DP 2.7 Gbps DP_LINK_BW value on g4x (Ville)

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- Fix return value on intel_atomic_commit_fence_wait (Aakash)
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Merge tag 'drm-intel-fixes-2025-07-24' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes

- Fix DP 2.7 Gbps DP_LINK_BW value on g4x (Ville)
- Fix return value on intel_atomic_commit_fence_wait (Aakash)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/aIJE9F-PcCe35PFb@intel.com
This commit is contained in:
Dave Airlie 2025-07-25 10:57:21 +10:00
commit e6b39e516c
2 changed files with 8 additions and 1 deletions
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3
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -7061,7 +7061,8 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat
struct drm_i915_private *i915 = to_i915(intel_state->base.dev);
struct drm_plane *plane;
struct drm_plane_state *new_plane_state;
int ret, i;
long ret;
int i;
for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
if (new_plane_state->fence) {

6
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -1604,6 +1604,12 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
u8 *link_bw, u8 *rate_select)
{
struct intel_display *display = to_intel_display(intel_dp);
/* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */
if (display->platform.g4x && port_clock == 268800)
port_clock = 270000;
/* eDP 1.4 rate select method. */
if (intel_dp->use_rate_select) {
*link_bw = 0;