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accel/amdxdna: Add AIE4 firmware loading
Add support for loading AIE4 firmware through the common PSP interfaces. Compared to AIE2, AIE4 introduces an additional CERT firmware image. aiem_psp_create() performs CERT setup when the CERT image size is non-zero. Co-developed-by: Hayden Laccabue <Hayden.Laccabue@amd.com> Signed-off-by: Hayden Laccabue <Hayden.Laccabue@amd.com> Signed-off-by: David Zhang <yidong.zhang@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://patch.msgid.link/20260330163705.3153647-5-lizhi.hou@amd.com
This commit is contained in:
David Zhang
Lizhi Hou
parent
dd2f592b55
commit
e69ef21408
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@ -57,7 +57,11 @@ struct aie_bar_off_pair {
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struct psp_config {
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const void *fw_buf;
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u32 fw_size;
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const void *certfw_buf;
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u32 certfw_size;
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void __iomem *psp_regs[PSP_MAX_REGS];
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u32 arg2_mask;
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u32 notify_val;
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};
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/* aie.c */
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@ -549,6 +549,8 @@ static int aie2_init(struct amdxdna_dev *xdna)
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psp_conf.fw_size = fw->size;
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psp_conf.fw_buf = fw->data;
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psp_conf.arg2_mask = GENMASK(23, 0);
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psp_conf.notify_val = 1;
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for (i = 0; i < PSP_MAX_REGS; i++)
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psp_conf.psp_regs[i] = tbl[PSP_REG_BAR(ndev, i)] + PSP_REG_OFF(ndev, i);
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ndev->aie.psp_hdl = aiem_psp_create(&xdna->ddev, &psp_conf);
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@ -6,11 +6,14 @@
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#include <drm/amdxdna_accel.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_print.h>
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#include <linux/firmware.h>
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#include <linux/sizes.h>
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#include "aie4_pci.h"
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#include "amdxdna_pci_drv.h"
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#define NO_IOHUB 0
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#define NO_IOHUB 0
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#define PSP_NOTIFY_INTR 0xD007BE11
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/*
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* The management mailbox channel is allocated by firmware.
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@ -207,13 +210,12 @@ static int aie4_mailbox_init(struct amdxdna_dev *xdna)
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static void aie4_fw_unload(struct amdxdna_dev_hdl *ndev)
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{
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/* TODO */
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aie_psp_stop(ndev->aie.psp_hdl);
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}
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static int aie4_fw_load(struct amdxdna_dev_hdl *ndev)
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{
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/* TODO */
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return 0;
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return aie_psp_start(ndev->aie.psp_hdl);
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}
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static int aie4_hw_start(struct amdxdna_dev *xdna)
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@ -261,11 +263,90 @@ static void aie4_hw_stop(struct amdxdna_dev *xdna)
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aie4_fw_unload(ndev);
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}
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static int aie4_request_firmware(struct amdxdna_dev_hdl *ndev,
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const struct firmware **npufw,
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const struct firmware **certfw)
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{
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struct amdxdna_dev *xdna = ndev->aie.xdna;
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struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
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char fw_name[128];
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int ret;
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ret = snprintf(fw_name, sizeof(fw_name), "amdnpu/%04x_%02x/%s",
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pdev->device, pdev->revision, ndev->priv->npufw_path);
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if (ret >= sizeof(fw_name)) {
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XDNA_ERR(xdna, "npu firmware path is truncated");
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return -EINVAL;
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}
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ret = request_firmware(npufw, fw_name, &pdev->dev);
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if (ret) {
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XDNA_ERR(xdna, "failed to request_firmware %s, ret %d", fw_name, ret);
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return ret;
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}
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ret = snprintf(fw_name, sizeof(fw_name), "amdnpu/%04x_%02x/%s",
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pdev->device, pdev->revision, ndev->priv->certfw_path);
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if (ret >= sizeof(fw_name)) {
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XDNA_ERR(xdna, "cert firmware path is truncated");
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ret = -EINVAL;
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goto release_npufw;
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}
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ret = request_firmware(certfw, fw_name, &pdev->dev);
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if (ret) {
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XDNA_ERR(xdna, "failed to request_firmware %s, ret %d", fw_name, ret);
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goto release_npufw;
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}
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return 0;
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release_npufw:
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release_firmware(*npufw);
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return ret;
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}
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static void aie4_release_firmware(struct amdxdna_dev_hdl *ndev,
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const struct firmware *npufw,
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const struct firmware *certfw)
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{
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release_firmware(certfw);
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release_firmware(npufw);
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}
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static int aie4_prepare_firmware(struct amdxdna_dev_hdl *ndev,
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const struct firmware *npufw,
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const struct firmware *certfw,
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void __iomem *tbl[PCI_NUM_RESOURCES])
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{
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struct amdxdna_dev *xdna = ndev->aie.xdna;
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struct psp_config psp_conf;
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int i;
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psp_conf.fw_size = npufw->size;
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psp_conf.fw_buf = npufw->data;
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psp_conf.certfw_size = certfw->size;
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psp_conf.certfw_buf = certfw->data;
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psp_conf.arg2_mask = ~0;
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psp_conf.notify_val = PSP_NOTIFY_INTR;
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for (i = 0; i < PSP_MAX_REGS; i++)
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psp_conf.psp_regs[i] = tbl[PSP_REG_BAR(ndev, i)] + PSP_REG_OFF(ndev, i);
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ndev->aie.psp_hdl = aiem_psp_create(&xdna->ddev, &psp_conf);
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if (!ndev->aie.psp_hdl) {
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XDNA_ERR(xdna, "failed to create psp");
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return -ENOMEM;
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}
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return 0;
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}
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static int aie4_pcidev_init(struct amdxdna_dev_hdl *ndev)
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{
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struct amdxdna_dev *xdna = ndev->aie.xdna;
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struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
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void __iomem *tbl[PCI_NUM_RESOURCES] = {0};
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const struct firmware *npufw, *certfw;
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unsigned long bars = 0;
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int ret, i;
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@ -282,6 +363,8 @@ static int aie4_pcidev_init(struct amdxdna_dev_hdl *ndev)
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return ret;
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}
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for (i = 0; i < PSP_MAX_REGS; i++)
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set_bit(PSP_REG_BAR(ndev, i), &bars);
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set_bit(xdna->dev_info->mbox_bar, &bars);
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set_bit(xdna->dev_info->sram_bar, &bars);
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@ -300,6 +383,15 @@ static int aie4_pcidev_init(struct amdxdna_dev_hdl *ndev)
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pci_set_master(pdev);
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ret = aie4_request_firmware(ndev, &npufw, &certfw);
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if (ret)
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goto clear_master;
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ret = aie4_prepare_firmware(ndev, npufw, certfw, tbl);
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aie4_release_firmware(ndev, npufw, certfw);
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if (ret)
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goto clear_master;
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ret = aie4_irq_init(xdna);
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if (ret)
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goto clear_master;
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@ -14,9 +14,13 @@
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#include "amdxdna_mailbox.h"
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struct amdxdna_dev_priv {
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const char *npufw_path;
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const char *certfw_path;
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u32 mbox_bar;
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u32 mbox_rbuf_bar;
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u64 mbox_info_off;
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struct aie_bar_off_pair psp_regs_off[PSP_MAX_REGS];
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};
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struct amdxdna_dev_hdl {
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@ -18,6 +18,7 @@
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#define PSP_VALIDATE 1
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#define PSP_START 2
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#define PSP_RELEASE_TMR 3
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#define PSP_VALIDATE_CERT 4
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/* PSP special arguments */
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#define PSP_START_COPY_FW 1
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@ -27,10 +28,20 @@
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#define PSP_ERROR_BAD_STATE 0xFFFF0007
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#define PSP_FW_ALIGN 0x10000
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#define PSP_CFW_ALIGN 0x8000
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#define PSP_POLL_INTERVAL 20000 /* us */
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#define PSP_POLL_TIMEOUT 1000000 /* us */
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#define PSP_REG(p, reg) ((p)->psp_regs[reg])
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#define PSP_REG(p, reg) ((p)->conf.psp_regs[reg])
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#define PSP_SET_CMD(psp, reg_vals, cmd, arg0, arg1, arg2) \
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({ \
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u32 *_regs = reg_vals; \
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u32 _cmd = cmd; \
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_regs[0] = _cmd; \
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_regs[1] = arg0; \
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_regs[2] = arg1; \
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_regs[3] = ((arg2) | ((_cmd) << 24)) & (psp)->conf.arg2_mask; \
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})
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struct psp_device {
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struct drm_device *ddev;
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@ -38,7 +49,9 @@ struct psp_device {
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u32 fw_buf_sz;
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u64 fw_paddr;
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void *fw_buffer;
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void __iomem *psp_regs[PSP_MAX_REGS];
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u32 certfw_buf_sz;
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u64 certfw_paddr;
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void *certfw_buffer;
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};
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static int psp_exec(struct psp_device *psp, u32 *reg_vals)
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@ -47,13 +60,22 @@ static int psp_exec(struct psp_device *psp, u32 *reg_vals)
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int ret, i;
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u32 ready;
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/* Check for PSP ready before any write */
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ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_STATUS_REG), ready,
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FIELD_GET(PSP_STATUS_READY, ready),
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PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT);
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if (ret) {
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drm_err(psp->ddev, "PSP is not ready, ret 0x%x", ret);
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return ret;
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}
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/* Write command and argument registers */
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for (i = 0; i < PSP_NUM_IN_REGS; i++)
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writel(reg_vals[i], PSP_REG(psp, i));
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/* clear and set PSP INTR register to kick off */
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writel(0, PSP_REG(psp, PSP_INTR_REG));
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writel(1, PSP_REG(psp, PSP_INTR_REG));
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writel(psp->conf.notify_val, PSP_REG(psp, PSP_INTR_REG));
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/* PSP should be busy. Wait for ready, so we know task is done. */
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ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_STATUS_REG), ready,
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@ -90,69 +112,124 @@ int aie_psp_waitmode_poll(struct psp_device *psp)
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void aie_psp_stop(struct psp_device *psp)
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{
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u32 reg_vals[PSP_NUM_IN_REGS] = { PSP_RELEASE_TMR, };
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u32 reg_vals[PSP_NUM_IN_REGS];
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int ret;
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PSP_SET_CMD(psp, reg_vals, PSP_RELEASE_TMR, 0, 0, 0);
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ret = psp_exec(psp, reg_vals);
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if (ret)
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drm_err(psp->ddev, "release tmr failed, ret %d", ret);
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}
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int aie_psp_start(struct psp_device *psp)
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static int psp_validate_fw(struct psp_device *psp, u8 cmd, u64 paddr, u32 buf_sz)
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{
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u32 reg_vals[PSP_NUM_IN_REGS];
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int ret;
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reg_vals[0] = PSP_VALIDATE;
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reg_vals[1] = lower_32_bits(psp->fw_paddr);
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reg_vals[2] = upper_32_bits(psp->fw_paddr);
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reg_vals[3] = psp->fw_buf_sz;
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PSP_SET_CMD(psp, reg_vals, cmd, lower_32_bits(paddr),
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upper_32_bits(paddr), buf_sz);
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ret = psp_exec(psp, reg_vals);
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if (ret) {
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if (ret)
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drm_err(psp->ddev, "failed to validate fw, ret %d", ret);
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return ret;
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}
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memset(reg_vals, 0, sizeof(reg_vals));
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reg_vals[0] = PSP_START;
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reg_vals[1] = PSP_START_COPY_FW;
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return ret;
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}
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static int psp_start(struct psp_device *psp)
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{
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u32 reg_vals[PSP_NUM_IN_REGS];
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int ret;
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PSP_SET_CMD(psp, reg_vals, PSP_START, PSP_START_COPY_FW, 0, 0);
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ret = psp_exec(psp, reg_vals);
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if (ret) {
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if (ret)
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drm_err(psp->ddev, "failed to start fw, ret %d", ret);
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return ret;
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}
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return 0;
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return ret;
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}
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int aie_psp_start(struct psp_device *psp)
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{
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int ret;
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ret = psp_validate_fw(psp, PSP_VALIDATE,
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psp->fw_paddr, psp->fw_buf_sz);
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if (ret)
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return ret;
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if (!psp->certfw_buf_sz)
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goto psp_start;
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ret = psp_validate_fw(psp, PSP_VALIDATE_CERT,
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psp->certfw_paddr, psp->certfw_buf_sz);
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if (ret)
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return ret;
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psp_start:
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return psp_start(psp);
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}
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/*
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* PSP requires host physical address to load firmware.
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* Allocate a buffer, obtain its physical address, align, and copy data in.
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*/
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static void *psp_alloc_fw_buf(struct psp_device *psp, const void *fw_data,
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u32 fw_size, u32 align, u32 *buf_sz,
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u64 *paddr)
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{
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u32 alloc_sz;
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void *buffer;
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u64 offset;
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*buf_sz = ALIGN(fw_size, align);
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alloc_sz = *buf_sz + align;
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buffer = drmm_kmalloc(psp->ddev, alloc_sz, GFP_KERNEL);
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if (!buffer)
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return NULL;
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*paddr = virt_to_phys(buffer);
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offset = ALIGN(*paddr, align) - *paddr;
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*paddr += offset;
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memcpy(buffer + offset, fw_data, fw_size);
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return buffer;
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}
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struct psp_device *aiem_psp_create(struct drm_device *ddev, struct psp_config *conf)
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{
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struct psp_device *psp;
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u64 offset;
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psp = drmm_kzalloc(ddev, sizeof(*psp), GFP_KERNEL);
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if (!psp)
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return NULL;
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psp->ddev = ddev;
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memcpy(psp->psp_regs, conf->psp_regs, sizeof(psp->psp_regs));
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psp->fw_buffer = psp_alloc_fw_buf(psp, conf->fw_buf, conf->fw_size,
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PSP_FW_ALIGN, &psp->fw_buf_sz,
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&psp->fw_paddr);
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if (!psp->fw_buffer)
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return NULL;
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psp->fw_buf_sz = ALIGN(conf->fw_size, PSP_FW_ALIGN);
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psp->fw_buffer = drmm_kmalloc(ddev, psp->fw_buf_sz + PSP_FW_ALIGN, GFP_KERNEL);
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if (!psp->fw_buffer) {
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drm_err(ddev, "no memory for fw buffer");
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if (!conf->certfw_size) {
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drm_dbg(ddev, "no cert fw");
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goto done;
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}
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/* CERT firmware */
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psp->certfw_buffer = psp_alloc_fw_buf(psp, conf->certfw_buf,
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conf->certfw_size, PSP_CFW_ALIGN,
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&psp->certfw_buf_sz,
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&psp->certfw_paddr);
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if (!psp->certfw_buffer) {
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drm_err(ddev, "no memory for cert fw buffer");
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return NULL;
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}
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/*
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* AMD Platform Security Processor(PSP) requires host physical
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* address to load NPU firmware.
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*/
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psp->fw_paddr = virt_to_phys(psp->fw_buffer);
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offset = ALIGN(psp->fw_paddr, PSP_FW_ALIGN) - psp->fw_paddr;
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psp->fw_paddr += offset;
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memcpy(psp->fw_buffer + offset, conf->fw_buf, conf->fw_size);
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done:
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memcpy(&psp->conf, conf, sizeof(psp->conf));
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return psp;
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}
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@ -16,6 +16,15 @@
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/* PCIe BAR Index for NPU3 */
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#define NPU3_REG_BAR_INDEX 0
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#define NPU3_PSP_BAR_INDEX 4
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#define MMNPU_APERTURE3_BASE 0x3810000
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#define NPU3_PSP_BAR_BASE MMNPU_APERTURE3_BASE
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#define MPASP_C2PMSG_123_ALT_1 0x3810AEC
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||||
#define MPASP_C2PMSG_156_ALT_1 0x3810B70
|
||||
#define MPASP_C2PMSG_157_ALT_1 0x3810B74
|
||||
#define MPASP_C2PMSG_73_ALT_1 0x3810A24
|
||||
|
||||
static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
|
||||
{ .major = 5, .min_minor = 10 },
|
||||
|
|
@ -23,14 +32,27 @@ static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
|
|||
};
|
||||
|
||||
static const struct amdxdna_dev_priv npu3_dev_priv = {
|
||||
.npufw_path = "npu.dev.sbin",
|
||||
.certfw_path = "cert.dev.sbin",
|
||||
.mbox_bar = NPU3_MBOX_BAR,
|
||||
.mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR,
|
||||
.mbox_info_off = NPU3_MBOX_INFO_OFF,
|
||||
.psp_regs_off = {
|
||||
DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1),
|
||||
DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU3_PSP, MPASP_C2PMSG_156_ALT_1),
|
||||
DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU3_PSP, MPASP_C2PMSG_157_ALT_1),
|
||||
DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1),
|
||||
DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU3_PSP, MPASP_C2PMSG_73_ALT_1),
|
||||
DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1),
|
||||
DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU3_PSP, MPASP_C2PMSG_156_ALT_1),
|
||||
/* npu3 doesn't use 8th pwaitmode register */
|
||||
},
|
||||
};
|
||||
|
||||
const struct amdxdna_dev_info dev_npu3_pf_info = {
|
||||
.mbox_bar = NPU3_MBOX_BAR,
|
||||
.sram_bar = NPU3_MBOX_BUFFER_BAR,
|
||||
.psp_bar = NPU3_PSP_BAR_INDEX,
|
||||
.vbnv = "RyzenAI-npu3-pf",
|
||||
.device_type = AMDXDNA_DEV_TYPE_PF,
|
||||
.dev_priv = &npu3_dev_priv,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user