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mmc: rk_sdmmc: manually zero desc after allocated on ARM64 platform.

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ARM64 call dmam_alloc_coherent mathod to allocate descriptor
will not auto clear buffer. So mmc may get wrong d->desc1 calculated that
load wrong address for BUF2 for dual-buf mode if NO CH set in d->desc0.
Then IDMAC will halt for BUF2 in WR_REQ_WAIT state and cannot generate
TI/RI or others in combine-interrupt.

Signed-off-by: lintao <lintao@rock-chips.com>
This commit is contained in:
lintao 2014-12-24 15:43:20 +08:00 committed by Huang, Tao
parent 1b4317b2c9
commit e68d16d336
1 changed files with 3 additions and 0 deletions
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3
drivers/mmc/host/rk_sdmmc.c
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@ -3627,6 +3627,9 @@ static void dw_mci_init_dma(struct dw_mci *host)
__func__);
goto no_dma;
}
#ifdef CONFIG_ARM64
memset(host->sg_cpu, 0, PAGE_SIZE);
#endif
/* Determine which DMA interface to use */
#if defined(CONFIG_MMC_DW_IDMAC)